CS8422-CNZ Cirrus Logic Inc, CS8422-CNZ Datasheet
CS8422-CNZ
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CS8422-CNZ Summary of contents
Page 1
... Format Detect Control Port & Registers Level Translators RMCK SDA/ SCL/ AD1/ AD0/ CDOUT CCLK CDIN CS Copyright Cirrus Logic, Inc. 2010 (All Rights Reserved) CS8422 SDOUT1 Serial Audio OSCLK1 3:1 Output OLRCK1 MUX TDM_IN SDOUT2 Serial 3:1 Audio OSCLK2 MUX ...
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... The CS8422 is available in a space-saving QFN pack- age in both Commercial (-40° +85° C) and Automotive (-40° +105° C) grades. The CDB4822 is also available for device evaluation and implementa- tion suggestions. Please refer to “ ...
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... Software Mode ...................................................................................................................... 32 6.6.2 Hardware Mode Control ........................................................................................................ 33 6.7 Non-Audio Detection ...................................................................................................................... 33 6.7.1 Hardware Mode Control ........................................................................................................ 34 6.7.2 Software Mode Control .......................................................................................................... 34 6.8 Format Detection (Software Mode Only) ....................................................................................... 34 6.9 Interrupts (Software Mode Only) .................................................................................................... 34 6.10 Channel Status and User Data Handling ..................................................................................... 34 6.10.1 Hardware Mode Control ...................................................................................................... 34 DS692F1 CS8422 3 ...
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... I²C Mode ................................................................................................................................ 43 9.1.3 Memory Address Pointer (MAP) ............................................................................................ 43 10. REGISTER QUICK REFERENCE ...................................................................................................... 44 11. SOFTWARE REGISTER BIT DEFINITIONS ...................................................................................... 47 11.1 CS8422 I.D. and Version Register (01h) ..................................................................................... 47 11.2 Clock Control (02h) ...................................................................................................................... 47 11.3 Receiver Input Control (03h) ........................................................................................................ 48 11.4 Receiver Data Control (04h) ........................................................................................................ 48 11.5 GPO Control 1 (05h) .................................................................................................................... 50 11 ...
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... Serial Copy Management System (SCMS) ......................................................................... 68 12.5 Jitter Attenuation .......................................................................................................................... 68 12.6 Jitter Tolerance ............................................................................................................................ 69 12.7 Group Delay ................................................................................................................................. 69 13. PERFORMANCE PLOTS ................................................................................................................... 70 14. PACKAGE DIMENSIONS .................................................................................................................. 79 15. THERMAL CHARACTERISTICS AND SPECIFICATIONS .............................................................. 79 16. ORDERING INFORMATION .............................................................................................................. 80 17. REFERENCES .................................................................................................................................... 80 18. REVISION HISTORY .......................................................................................................................... 81 DS692F1 CS8422 5 ...
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... Figure 13.TDM Master Mode Timing Diagram .......................................................................................... 28 Figure 14.TDM Slave Mode Timing Diagram ............................................................................................ 28 Figure 15.TDM Mode Configuration (All CS8422 outputs are slave) ........................................................ 28 Figure 16.TDM Mode Configuration (First CS8422 output is master, all others are slave) ....................... 28 Figure 17.Single-Ended Receiver Input Structure, Receiver Mode 1 ....................................................... 30 Figure 18.Differential Receiver Input Structure ......................................................................................... 31 Figure 19 ...
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... Figure 86.THD+N vs. Input Frequency – 0 dBFS, 48 kHz:44.1 kHz ......................................................... 78 Figure 87.THD+N vs. Input Frequency – 0 dBFS, 48 kHz:96 kHz ............................................................ 78 Figure 88.THD+N vs. Input Frequency – 0 dBFS, 44.1 kHz:48 kHz ......................................................... 78 Figure 89.THD+N vs. Input Frequency – 0 dBFS, 96 kHz:48 kHz ............................................................ 78 Figure 90.Total Power Supply Current vs. Differential Mode Receiver Input Sample Frequency ............. 78 DS692F1 CS8422 7 ...
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... Table 4. Hardware Mode Serial Audio Format Control ............................................................................. 41 Table 5. Hardware Mode Serial Audio Port Clock Control ........................................................................ 41 Table 6. Summary of Software Register Bits ............................................................................................ 44 Table 7. GPO Pin Configurations .............................................................................................................. 50 Table 8. ISCLK/ILRCK Ratios and SISF Settings ..................................................................................... 53 Table 9. OSCLK1/OLRCK1 Ratios and SOSF1 Settings .......................................................................... 54 Table 10. OSCLK2/OLRCK2 Ratios and SOSF2 Settings ........................................................................ 55 8 CS8422 DS692F1 ...
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... Software Clock (Input) - Serial control interface clock used to clock control data bits into and out of SCL/CCLK 9 the CS8422. Serial Control Data I/O (I²C) / Data Out (SPI) (Input/Output I²C Mode, SDA is the control I/O SDA/CDOUT 10 data line. In SPI Mode, CDOUT is the output data from the control port interface on the CS8422. DS692F1 ...
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... Fs, where Fs is the sample rate of the incoming AES3- compatible data, or ISCLK/64. Reset (Input) - When RST is low the CS8422 enters a low power mode and all internal states are RST 32 reset. On initial power up RST must be held low until the power supply is stable and all input clocks are stable in frequency and phase ...
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... Crystal Out (Output) - Crystal output for Master clock. See DS692F1 Thermal Pad Top-Down View 32-Pin QFN Package Pin Description Table 4 on page 41 for format settings. Table 5 on page 41 for format settings. CS8422 25 OSCLK2 24 SDOUT2 DGND 21 VD_FILT 20 V_REG 19 TX “SRC Master Clock” “SRC Master Clock” on page 38. 11 ...
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... k pull- present on this pin, the SDOUT1 MCLK source will be RMCK, otherwise it will be the clock input through XTI-XTO. Reset (Input) - When RST is low the CS8422 enters a low power mode and all internal states are RST 32 reset. On initial power up RST must be held low until the power supply is stable and all input clocks are stable in frequency and phase ...
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... Transient currents 100 mA will not cause SCR latch-up. DS692F1 Symbol VL VA V_REG Commercial Grade T A Automotive Grade Symbol VL VA V_REG (Note stg CS8422 Min Nominal Max Units 1.71 3.3 5.25 V 3.135 3.30 3.465 V 3.135 3.30 3.465 V -40 - +85 °C -40 - +105 °C Min ...
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... Fsi indicates the input sample rate. Fso indicates the output sample rate. Numbers separated by a colon indicate the ratio of Fsi to Fso. DIGITAL FILTER CHARACTERISTICS Parameter Passband (Upsampling or Downsampling) Passband Ripple Stopband (Downsampling) Stopband Attenuation Group Delay 14 CS8422 Min Typ Max Slave XTI/2048 - ...
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... AES3 receiver output. DS692F1 Min Typ VA - 4.7 V_REG - 102 15.2 V_REG - 5 32.4 V_REG - CS8422 Max Units - µA - µA - µA - µA - µA - µ ...
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... Maximum sensitivity in accordance with AES3-2003 section 8.3.3. Measured with eye diagram height at the specified voltage and width of at least 50% of one-half the biphase symbol period. 16 Symbol (Note CS8422 Min Typ Max Units + 200 mVpp - 11 - k 200 ...
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... Symbol (Note 8) Differential RX Mode Single-Ended RX Mode Crystal Digital Clock Source sckh t sckl t sckh t sckl t lcks t lckd t dpd lrckh t fss t fsh t lcks t dpd CS8422 Min Typ Max Units 216 - 200 - ps RMS - 475 - ps RMS 12 - 27.000 MHz 1.024 - 49.152 MHz 49.152 MHz 49.152 MHz 9 ...
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... TDM Mode OSCLK Falling Edge to OLRCK Edge (VL = 1.8V) TDM Mode OSCLK Falling Edge to OLRCK Edge (VL = 2.5V) Notes: 7. After powering up the CS8422, RST should be held low until the power supplies and clocks are settled ISCLK is selected as the clock source for the PLL, then the Sample Rate = ISCLK/64. 18 ...
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... OSCLK (input) MSB MSB-1 TDM_IN (input) MSB MSB-1 SDOUT (output) Figure 2. TDM Slave Mode Timing OLRCK (output) t fsm OSCLK (output) MSB-1 SDOUT (output) MSB-1 Figure 4. TDM Master Mode Timing CS8422 t lrckh fsh sckh sckl MSB t dpd MSB t dpd MSB MSB-1 MSB-1 ...
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... CDIN CDOUT pF. L Symbol f sck t srs t spi t csh t css t scl t sch t dsu scdov t cscdo srs t spi t css t scl t sch dsu scdov t scdov Figure 5. SPI Mode Timing CS8422 Min Max Unit 0 6.0 MHz 500 - µs 500 - ns 1.0 - µ 100 ns - 100 100 ns - 100 all other times ...
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... L Symbol f scl t irs t buf t hdst t low t high t sust t (Note 17) hdd t sud susp t ack t high t t sud t ack hdd Figure 6. I²C Mode Timing CS8422 Min Max - 100 500 - 4.7 - 4.0 - 4.7 - 4 250 - - 1000 rd - 300 fd 4.7 - 300 1000 , of SCL ate ...
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... AD0/CS GPO3 30 8 AD1/CDIN GPO2 18 9 SCL/CCLK GPO1 17 10 SDA/CDOUT GPO0 16 32 RST 4 21 CS8422 +1.8V to +5V 0.1 µF 20 0.1 µF 10 µF + Serial Audio Input Device TDM Output Device Serial Audio Input Device +VL 20 k Clock Routing, Interrupt Control, Channel-Status, and ...
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... RCBL MCLK_OUT 30 SRC_UNLOCK OLRCK2 25 OSCLK2 24 SDOUT2 23 8 MS_SEL 7 SAOF RMCK 14 TX_SEL 15 RX_SEL XTO 12 32 RST 21 4 CS8422 +1.8V to +5V 0.1 µF 20 0.1 µF 10 µF + +VL 20 k 27 Serial Audio Input Device 29 TDM Output Device +VL 20 k 13 Serial Audio Input Device +VL 20 k ...
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... XTI, or synchronous to the master clock re- covered from the incoming S/PDIF or AES3 data. CS8422 can be controlled either in Software Mode stand-alone Hardware Mode. In Software Mode, the user can control the device through either a SPI or I²C control port. ...
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... In Hardware Mode, there are always 64 SCLK periods per LRCK period when a serial port is set to master mode. 5.1.4 Software Mode Control In Software Mode, the CS8422 provides a serial audio input port and two serial audio output ports. Each serial port’s clocking and data routing options are fully configurable as shown in Format (0Bh), ...
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... Figure 11. Serial Audio Interface Format – Right-Justified (Master Mode only) OLRCK Channel A OSCLK SDOUT LSB MSB Figure 12. Serial Audio Interface Format – AES3 Direct Output LSB MSB MSB LSB MSB Extended LSB CS8422 Channel B MSB Channel B MSB Channel B MSB LSB MSB LSB Channel B MSB DS692F1 ...
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... In TDM Mode, the TDM_IN pin is used to input TDM-formatted data while the SDOUT1 or SDOUT2 (Soft- ware Mode only) pin is used to output TDM data. If the CS8422 is the first TDM device in the chain, it should have its TDM_IN connected to GND. Data is transmitted from SDOUTx (SDOUT1 or SDOUT2) most significant bit first on the first falling OSCLKx edge after an OLRCKx rising edge and is valid on the rising edge of OSCLKx ...
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... OSCLK TDM_IN SDOUT ILRCK ISCLK Master SDIN OLRCK OSCLK SDOUT OLRCK OSCLK PCM Source 1 PCM Source 2 Figure 16. TDM Mode Configuration (First CS8422 output is master, all others are slave) 28 MSB MSB MSB SDOUT SDOUT SDOUT OSCLKs 32 OSCLKs 32 OSCLKs MSB MSB MSB SDOUT ...
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... The CS8422 includes a digital interface receiver that can receive and decode audio data according to the AES3, IEC60958, S/PDIF, and EIJ CP1201 interface standards. The CS8422 uses either a 4:1 single-ended or 2:1 differential input mux to select the input pin(s) that will receive input data to be decoded. A low-jitter clock (RMCK) is recovered using a PLL, which provides the digital interface receiver with a master clock ...
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... AC coupling capacitors, as mentioned in of the receiver in differential mode. 30 for more details). Figure 17 shows the input structure of the VA (22000/N) 22 k (22000/N) 22 k AGND /V apply (see IH IL Section 6.2.2.1. Figure 18 CS8422 “Switching Spec- shows the structure DS692F1 ...
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... Recovered Master Clock - RMCK The CS8422 has an internal PLL which recovers a high-frequency system clock, referred to as the recov- ered master clock (RMCK). RMCK can be generated by incoming AES3-compatible data or the ISCLK (slave mode and Software Mode only). This clock is used as the master clock source for the AES3 receiver and the master-mode serial port that it directly supplies data to, and is available as an output on the RMCK pin ...
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... OLRCK (depending on the serial port interface format setting) will be treated as being sampled at the same time. Since the CS8422 has no control of the OLRCK in slave mode, the latency of the data through the part will be a multiple of 1/Fs plus the intrinsic delay between OL- RCK and the preambles also present in master mode ...
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... CS8422. However, certain non-audio sources, such as AC-3 MPEG encoders, may not adhere to this convention and the bit may not be properly set. The CS8422 AES3 receiver can detect such non-audio data through the use of an auto-detect module. The auto-detect module is similar to auto-detect software used in Cirrus Logic DSPs ...
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... Format Detection (Software Mode Only) In Software Mode, the CS8422 can automatically detect various serial audio input formats. The Format De- tect Status register (12h) is used to indicate a detected format. The register will indicate if uncompressed PCM data, IEC61937 data, DTS_LD data, DTS_CD data, or digital silence was detected. Additionally, the IEC61937 Pc/Pd burst preambles are available in registers 2Dh-30h ...
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... OLRCK1 RX OLRCK2 SRC AES FRAMES Table 1. VLRCK Behavior “Serial Audio Output Data Format - SDOUT1 (0Ch)” (0Dh)”. The appropriate bits can be stripped from the SDOUT register. CS8422 registers. OLRCK and RCBL can be COMMENT see (Note 4) see (Note 4) see (Note 4) see (Note 6) “ ...
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... VLRCK edge and will be valid on VLRCK edges ( OSCLK period serial port is not sourced directly by the AES3-compatible receiver ( sample rate conversion application), the data will transition 1/64*Fsi after a VLRCK edge, and will be valid on VLRCK edges (t = 1/64*Fsi). 36 192 AES3 Frames C/U[1] t Figure 19. C/U Data Outputs CS8422 C/U[383] DS692F1 ...
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... When using the serial audio input port in left justified and I²S Modes, all input data is treated as 24-bits wide. Any truncation that has been done prior to the CS8422 to less than 24-bits should have been done using an appropriate dithering process. If the serial audio input port is in Right-Justified Mode, the input data will be truncated to the bit depth set through the is set to 16 bits, and the input data is 24-bits wide, then truncation distortion will occur ...
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... The CS8422 has the ability to operate without a master clock input through XTI. This benefits the design by not requiring extra external clock components (lowering production cost) and not requiring a master clock to be routed to the CS8422, resulting in lowered noise contribution in the system. In this mode, an internal oscillator provides the clock to run all of the internal logic. See tion of how the SRC MCLK can be selected ...
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... Clock Control (08h)” on page 51 8. HARDWARE MODE CONTROL The CS8422 provides a stand-alone hardware control mode in which the part does not require an I²C or SPI control port. In Hardware Mode, the user is provided with a subset of the features available in Software Mode as shown in Figure 21. The part will be in Hardware Mode if there k ...
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... Hardware Mode Serial Audio Port Control The CS8422 uses the resistors attached to the MS_SEL and SAOF pins to determine the modes of opera- tion for its serial output ports. After RST is released, the resistor value and condition (VL or GND) are sensed. This operation will take approximately complete. The SRC_UNLOCK pin will remain high and both SDOUT pins will be muted until the mode detection sequence has completed ...
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... Slave Master, Fso = MCLK/128 RMCK = 256 x Fsi Master, Fso = MCLK/256 Master, Fso = MCLK/512 Slave Master, Fso = MCLK/128 RMCK = 512 x Fsi Master, Fso = MCLK/256 Master, Fso = MCLK/512 CS8422 SDOUT2 Data Format I²S I²S I²S Left-Justified Left-Justified Left-Justified Right-Justified (Master mode only) Right-Justified ...
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... SPI Mode In SPI Mode the CS8422 chip select signal, CCLK is the control port bit clock (input into the CS8422 from the microcontroller), CDIN is the input data line from the microcontroller, CDOUT is the output data line to the microcontroller. Data is clocked in on the rising edge of CCLK and out on the falling edge. ...
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... SDA while the clock is high. A Stop condition is a rising transition while the clock is high. All other transitions of SDA occur while the clock is low. The first byte sent to the CS8422 after a Start condition consists of a 7-bit chip address field and a R/W bit (high for a read, low for a write). ...
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... SISF SIFSEL2 SIFSEL1 SOSF1 SORES1_1 SORES1_0 SOFSEL1_1 SOFSEL1_0 SOSF2 SORES2_1 SORES2_0 SOFSEL2_1 SOFSEL2_0 QCRCM CCRCM UNLOCKM OSLIPM DETCM CCHM Reserved Reserved CS8422 ID0 REV2 REV1 RMCK_ INT1 INT0 CTL0 INPUT_ TXSEL0 Reserved TYPE EMPH_ EMPH_ DETCI CNTL2 CNTL1 GPO1SEL2 GPO1SEL1 GPO3SEL1 ...
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... AC1[4] AC2[6] AC2[5] AC2[4] AC3[6] AC3[5] AC3[4] AC4[6] AC4[5] AC4[4] BC0[6] BC0[5] BC0[4] BC1[6] BC1[5] BC1[4] BC2[6] BC2[5] BC2[4] BC3[6] BC3[5] BC3[4] CS8422 PRO COPY ORIG HD_CD DGTL_SIL Reserved V CONF BIP RERR QCH FCH 192KHZ Reserved Reserved BLK_CERR BLK_BERR FS_XT11 FS_XT10 ...
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... PD1[7] Byte 1 Table 6. Summary of Software Register Bits (Continued BC4[6] BC4[5] BC4[4] PC0[6] PC0[5] PC0[4] PC1[6] PC1[5] PC1[4] PD0[6] PD0[5] PD0[4] PD1[6] PD1[5] PD1[4] CS8422 BC4[3] BC4[2] BC4[1] PC0[3] PC0[2] PC0[1] PC1[3] PC1[2] PC1[1] PD0[3] PD0[2] PD0[1] PD1[3] PD1[2] PD1[1] 0 BC4[0] PC0[0] ...
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... PDN - Controls the internal clocks, allowing the CS8422 to be placed in a “powered down”, low current con- sumption state. This bit must be written to the 0 state to allow the CS8422 to begin operation. All input clocks should be stable in frequency and phase when PDN is set to 0. ...
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... Truncation occurs before the de-emphasis filter. TRUNC has no effect on output data is detected as being non-audio. HOLD[1:0] – Determine how received AES3 audio sample is affected when a receive error occurs 00 - hold last audio sample TXSEL1 TXSEL0 CHS DETCI CS8422 2 1 INPUT_TYPE Reserved Reserved EMPH_CNTL2 EMPH_CNTL1 EMPH_CNTL0 1 0 DS692F1 ...
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... Channel Status data indicates that no de-emphasis should be applied, de-emphasis will not be enabled. If data is detected as being non-audio, the de-emphasis filter will not be enabled. DS692F1 Figure 25 Gain dB T1=50 µs 0dB µs -10dB F1 F2 Frequency 3.183 kHz 10.61 kHz Figure 25. De-Emphasis Filter Response CS8422 for De-emphasis filter response. 49 ...
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... GPO2SEL0 GPO3SEL3 Definition Fixed low level Fixed VL level. State of EMPH bit in the incoming data stream CS8422 interrupt output Channel status bit User data bit Receiver Error Non-Validity Receiver Error Receiver Channel Status Block Defined in “PLL Status (15h)” on page Defined in “PLL Status (15h)” on page Non-audio indicator for decoded input stream Virtual LRCK, can be used to frame the C and U output data ...
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... OLRCK and OSCLK are derived from the MCLK selected in this register XTI-XTO DS692F1 SAO_CLK0 SAO_MCLK and CS8422 53). When set to master, ILRCK 2 1 SRC_MCLK1 SRC_MCLK0 SRC_DIV 0 0 “Serial Audio Output Data Format - SDOUT2 “Serial Audio Output Data Format - SDOUT1 55). When set to mas- ...
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... SRC_MUTE – When SRC_MUTE is set to ‘1’, the SRC will soft-mute when it loses lock and soft unmute when it regains lock Soft mute disabled 1 - Soft mute enabled 11.10 Data Routing Control(0Ah SDOUT1(1) SDOUT1(0) SDOUT2( SDOUT1[1:0] - Controls the data source for SDOUT1 RMCK0 SRC_MUTE SDOUT2(0) MUTESAO1 CS8422 “SRC Mas Reserved Reserved Reserved MUTESAO2 SRCD Reserved 0 0 DS692F1 ...
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... SISF - ISCLK Frequency. Valid only in master mode (SIMS = 1). Should be changed when PDN = 1. See Table 8 for details. SAI_CLK[3:0] 0000 0001 0010 0011 0100 Table 8. ISCLK/ILRCK Ratios and SISF Settings DS692F1 SIFSEL1 SIFSEL0 MCLK/ILRCK Ratio 64 96 128 192 256 CS8422 2 1 Reserved Reserved Reserved ISCLK/ILRCK Ratio SISF = 0 SISF = 1 64 INVALID 128 128 0 53 ...
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... Table 9. OSCLK1/OLRCK1 Ratios and SOSF1 Settings 54 384 512 768 1024 SORES1_0 SOFSEL1_1 MCLK/OLRCK1 Ratio 64 96 128 192 256 384 512 768 1024 CS8422 128 128 2 1 SOFSEL1_0 TDM1 0 0 OSCLK1/OLRCK1 Ratio SOSF1 = 0 SOSF1 = 1 64 INVALID 128 128 ...
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... Note: If serial output master mode and sourced directly by the serial input port, then SAI_CLK[3:0] determine the MCLK/OLRCK1 ratio. SAO_CLK[3:0], SAI_CLK[3:0], or RMCK[3:0] 0000 0001 Table 10. OSCLK2/OLRCK2 Ratios and SOSF2 Settings DS692F1 for more details SORES2_0 SOFSEL2_1 MCLK/OLRCK2 Ratio 64 96 CS8422 2 1 SOFSEL2_0 Reserved Reserved 0 OSCLK2/OLRCK2 Ratio SOSF2 = 0 SOSF2 = 1 64 INVALID ...
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... The bits of this register serve as a mask for the Interrupt Status register mask bit is set to 1, the error is unmasked, meaning that its occurrence will affect the INT pin and the status register mask bit is set 56 128 192 256 384 512 768 1024 UNLOCKM CCHM RERRM CS8422 64 128 128 128 128 CONFM BIPM PARM ...
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... Reserved PRO - Channel status block format indicator 0 - Received channel status block is in the consumer format. DS692F1 4 3 Reserved RERR1 AUX0 PRO “Receiver Data Control (04h)” on page CS8422 Section 11.5 on page 50 for more details RERR0 SRC_UNLOCK1 SRC_UNLOCK0 COPY ORIG EMPH 48. ...
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... Bits that are masked off in the receiver error mask register will always this register. QCRC - Q-subcode data CRC error indicator. Updated on Q-subcode block boundaries error Error DTS_CD HD_CD UNLOCK V CS8422 DGTL_SIL Reserved Reserved CONF BIP PAR DS692F1 ...
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... When the serial audio output port is in slave mode, and OLRCK is asynchronous to the port data source, this bit will go high every time a data sample is dropped or repeated. See on page 25 for more information. DS692F1 CCH RERR CS8422 QCH FCH SRC_UNLOCK “Serial Port Clock Operation” 59 ...
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... Indicates the frequency range of the sample rate of incoming AES3 data (Fsi). If Fsi 98 kHz, this bit will output a “0”. If Fsi 120 kHz, this bit will output a “1”. Otherwise the output is indeterminate 96KHZ 192KHZ CS8422 Reserved Reserved Reserved DS692F1 ...
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... There has been at least one biphase error associated with incoming AES3 data during the input of the last AES3 data block. BLK_PERR - Block Parity Error. Updated on DETC boundaries 0 - There has been no parity error associated with incoming AES3 data during the input of the last AES3 data block. DS692F1 RX_LOCK BLK_VERR - - - CS8422 BLK_CERR BLK_BERR BLK_PERR - - - 61 ...
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... AC4[6] AC4[5] AC4[4] BC0[7] BC0[6] BC0[5] BC0[4] BC1[7] BC1[6] BC1[5] BC1[4] BC2[7] BC2[6] BC2[5] BC2[4] BC3[7] BC3[6] BC3[5] BC3[4] BC4[7] BC4[6] BC4[5] BC4[4] CS8422 FS_XT10 FS_XT9 FS_XT8 FS_XT2 FS_XT1 FS_XT0 ADDRESS ADDRESS ADDRESS TRACK TRACK TRACK INDEX INDEX INDEX MINUTE MINUTE ...
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... Bit 7 Bit 6 Bit 5 Bit 4 PC0[7] PC0[6] PC0[5] PC0[4] PC1[7] PC1[6] PC1[5] PC0[4] PD0[7] PD0[6] PD0[5] PC0[4] PD1[7] PD1[6] PD1[5] PD1[4] CS8422 Bit 3 Bit 2 Bit 1 Bit 0 PC0[3] PC0[2] PC0[1] PC0[0] PC1[3] PC1[2] PC1[1] PC1[0] PD0[3] PD0[2] PD0[1] PD0[0] PD1[3] PD1[2] PD1[1] PD1[0] ...
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... Power Supply, Grounding, and PCB layout The CS8422 operates from +3.3 V and +5.0 V supply. These supplies may be set independently. Follow normal supply decoupling practices, see Extensive use of power and ground planes, ground plane fill in unused areas, and surface mount decoupling capacitors are recommended ...
Page 65
... Figure 31. TTL/CMOS Input Circuit – Differential Figures 32 and 33 illustrate how this should be done for both sin- CS8422 CS8422 0. See Text RXP0 110 0.01 F RXN0 CS8422 0.01 F RXP 75 RXN 0.01 F CS8422 0.01 F RXP RXN 0.01F Mode 65 ...
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... Channel Status Buffer Management 12.4.1 AES3 Channel Status (C) Bit Management The CS8422 contains sufficient RAM to store the first 5 bytes of C data for both A and B channels ( bits). The user may read from this buffer’s RAM through the control port. The buffering scheme involves two buffers, named D and E, as shown in represents the first bit in the serial C data stream ...
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... Accessing the E buffer The user can monitor the incoming data by reading the E buffer, which is mapped into the register space of the CS8422, through the control port. The user can configure the interrupt enable register to cause interrupts to occur whenever buffer transfers occur. This allows determination of the allowable time periods to interact with the E buffer. ...
Page 68
... Serial Copy Management System (SCMS) In Software Mode, the CS8422 allows read access to all the channel status bits. For consumer mode SCMS compliance, the host microcontroller needs to read and interpret the Category Code, Copy bit and L bit ap- propriately. In Hardware Mode, the SCMS protocol can be followed by using the C bit serial output pin. See Status and User Data Handling” ...
Page 69
... The group delay introduced by the CS8422 depends on the type of interface selected, and input and output sample rates of the sample rate converter. The expression for the group delay through the CS8422 with the use of the sam- ple rate converter is shown below, where the interface delay is 3 OLRCK periods in all modes except AES3 direct mode, in which OLRCK periods ...
Page 70
... Figure 42. Wideband FFT – 0 dBFS 1 kHz Tone, 48 kHz:96 kHz 15k 17.5k 20k 22. 15k 17.5k 20k 22. 30k 35k 40k 45k CS8422 + 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 -200 10k 20k 30k 40k 50k ...
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... -10 -20 -30 -40 -50 -60 -70 -80 - CS8422 Figure 45. Wideband FFT – -60 dBFS 1 kHz Tone, 48 kHz:96 kHz Figure 47. Wideband FFT – -60 dBFS 1 kHz Tone, 44.1 kHz:192 kHz Figure 49. Wideband FFT – -60 dBFS 1 kHz Tone, 48 kHz:44.1 kHz ...
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... kHz and 11 kHz -7 dBFS, 96 kHz:48 kHz + 0 -10 -20 -30 -40 -50 -60 -70 -80 - kHz and 11 kHz -7 dBFS, 48 kHz:44.1 kHz + 0 -10 -20 -30 -40 -50 -60 -70 -80 - CS8422 Figure 51. IMD – Figure 53. IMD – Figure 55. Wideband FFT – 0 dBFS 20 kHz Tone, 44.1 kHz:48 kHz DS692F1 ...
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... Tone, 48 kHz:44.1 kHz DS692F1 + 0 -10 -20 -30 -40 -50 -60 -70 -80 - -10 -20 -30 -40 -50 -60 -70 -80 - Figure 61. THD+N vs. Output Sample Rate – Figure 57. Wideband FFT – 0 dBFS 20 kHz Tone, 48 kHz:96 kHz 2 . Figure 59. Wideband FFT – 0 dBFS 20 kHz Tone, 96 kHz:48 kHz dBFS 1 kHz Tone, Fsi = 192 kHz CS8422 ...
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... Tone, Fsi = 32 kHz Figure 63. THD+N vs. Output Sample Rate – Figure 65. Dynamic Range vs. Output Sample Rate – Figure 67. Dynamic Range vs. Output Sample Rate – CS8422 dBFS 1 kHz Tone, Fsi = 96 kHz -60 dBFS 1 kHz Tone, Fsi = 192 kHz -60 dBFS 1 kHz Tone, Fsi = 32 kHz DS692F1 ...
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... Figure 72. Dynamic Range vs. Output Sample Rate – -60 dBFS 1 kHz Tone, Fsi = 48 kHz DS692F1 + Figure 69. Dynamic Range vs. Output Sample Rate – Figure 71. Passband Ripple – 192 kHz:48 kHz + -140 dBFS Input, 200 Hz Tone, 48 kHz:48 kHz CS8422 -60 dBFS 1 kHz Tone, Fsi = 44.1 kHz Figure 73. Linearity Error – ...
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... Input, 200 Hz Tone, 44.1 kHz:48 kHz -140 dBFS Input, 200 Hz Tone, 48 kHz:96 kHz + -140 dBFS Input, 200 Hz Tone, 44.1 kHz:192 kHz + -140 dBFS Input, 200 Hz Tone, 192 kHz:44.1 kHz CS8422 - Figure 75. Linearity Error – Figure 77. Linearity Error – Figure 79. Linearity Error – DS692F1 + ...
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... Figure 84. THD+N vs. Input Amplitude – 1 kHz Tone, 44.1 kHz:48 kHz DS692F1 - Figure 81. THD+N vs. Input Amplitude – Figure 83. THD+N vs. Input Amplitude – Figure 85. THD+N vs. Input Amplitude – CS8422 - kHz Tone, 48 kHz:96 kHz - kHz Tone, 44.1 kHz:192 kHz - kHz Tone, 192 kHz:48 kHz + ...
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... 20000 60000 100000 140000 Frequency (Hz) Figure 90. Total Power Supply Current vs. Differential Mode Receiver Input Sample Frequency Figure 87. THD+N vs. Input Frequency – Figure 89. THD+N vs. Input Frequency – 180000 220000 CS8422 dBFS, 48 kHz:96 kHz dBFS, 96 kHz:48 kHz DS692F1 ...
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... MAX MIN -- 0.0394 -- -- 0.0020 0.00 0.0118 0.20 0.1476 3.65 0.1476 3.65 0.0197 0.30 JEDEC #: MO-220 Controlling Dimension is Millimeters. Symbol JA CS8422 b e Pin #1 Corner L D2 Bottom View MILLIMETERS NOM MAX -- 1.00 -- 0.05 0.25 0.30 5.00 BSC 3.70 3.75 5.00 BSC 3.70 3 ...
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... Philips Semiconductor, “The I²C-Bus Specification: Version 2,” Dec. 1998. http://www.semiconductors.philips.com 80 Pb-Free Package Grade Range Commercial QFN YES Automotive +105°C - YES - CS8422 Temp Order# Container Rail CS8422-CNZ -40° to +85°C Tape and Reel CS8422-CNZR Rail CS8422-DNZ -40° to Tape and Reel CS8422-DNZR - - CDB8422 DS692F1 ...
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... PP2 Updated package dimensions in F1 Final Release Changed VA, VREG, and VL = 5.0 V normal operation values in Updated Figure 37 with test data from CS8422 Updated Figure 90 Updated hardware mode NVERR and RERR descriptions in Updated values in Switching Specifications Added TDM_IN pin not supported in master mode in Updated Section 11 ...
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... Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. AC registered trademark of Dolby Laboratories, Inc. DTS is a registered trademark of Digital Theater Systems, Inc. I² trademark of Philips Semiconductor. SPI is a trademark of Motorola, Inc. 82 CS8422 DS692F1 ...