CY14E256LA-SZ25XIT Cypress Semiconductor Corp, CY14E256LA-SZ25XIT Datasheet - Page 5

• Manufacturer Part Number: CY14E256LA-SZ25XIT
• Description: CY14E256LA-SZ25XIT
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY14E256LA-SZ25XIT

• Format - Memory: RAM
• Memory Type: NVSRAM (Non-Volatile SRAM)
• Memory Size: 256K (32K x 8)
• Speed: 25ns
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Details of Improvement
Hardware STORE Related Improvements
STORE Initiation)
The HSB pin of the nvSRAM is an open drain I/O pin used
to indicate or initiate a STORE operation. When a STORE
operation is in progress, nvSRAM pulls the HSB pin low to
indicate that the device is busy and cannot be accessed for
read/write operation. During normal operation, the HSB pin
can be pulled low to initiate a Hardware STORE operation.
As shown in
the HSB
CY14E256L/STK14C88 to CY14E256LA. All of these
changes
specification and should be considered as added benefits in
your system while converting to the new part number.
Write Latch: When a write operation is done, a ‘write latch’ is
set internally. When HSB is pulled low, nvSRAM checks
this write latch before initiating a STORE. This is done to
prevent any unnecessary loss of endurance cycles.
t
If a write latch is set and the HSB pin is pulled low,
CY14E256L/STK14C88 enables 1 us time for write
operations to complete before STORE operation begins and
October 5, 2009
HSB pin (Hardware STORE Busy Indication/Hardware
DELAY
Write Latch Set
are
pin input and output have changed from
Table
improvements
5, several timing parameters related to
Figure 1. CY14E256L/STK14C88: AC Parameters Related to HSB
from
Figure 2. CY14E256LA: AC Parameters Related to HSB
the
original
Document No. 001-55663 Rev. **
part
reads and writes are inhibited. This potentially enables
inadvertent data to be written to the nvSRAM during the
t
In CY14E256LA, the t
write cycle time for any ongoing write to complete after
security from inadvertent write operations.
Also, if HSB pin is pulled low externally for a minimum of
t
pulls the pin low only indicating a STORE operation within
25 ns (t
is not specified in the CY14E256L/STK14C88. (See
and
If no writes are performed since the last STORE/RECALL
operation, STORE operation does not start when HSB is
pulled low. However, the HSB pin is still internally pulled
low for 1 us (t
device.
CY14E256LA device does not pull the HSB pin low
internally if write latch is not set.
HSB pin is pulled low. This improvement provides better
HSB LOW when write latch not set:
DELAY
PHSB
Figure
time on CY14E256LA, the output driver of HSB pin
duration.
DELAY
2)
). This parameter for HSB low to STORE busy
DELAY
) time in the CY14E256L/ STK14C88
DELAY
Write Latch not Set
parameter enables only one
Figure 1
AN55663
5
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