CY62128EV30LL-45ZXIT Cypress Semiconductor Corp, CY62128EV30LL-45ZXIT Datasheet - Page 6

• Manufacturer Part Number: CY62128EV30LL-45ZXIT
• Description: CY62128EV30LL-45ZXIT
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY62128EV30LL-45ZXIT

• Format - Memory: RAM
• Memory Type: SRAM
• Memory Size: 1M (128K x 8)
• Speed: 45ns
• Interface: Parallel
• Voltage - Supply: 2.2 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-TSOP I
• Density: 1Mb
• Access Time (max): 45ns
• Sync/async: Asynchronous
• Architecture: Not Required
• Clock Freq (max): Not RequiredMHz
• Operating Supply Voltage (typ): 3V
• Address Bus: 17b
• Package Type: TSOP-I
• Operating Temp Range: -40C to 85C
• Number Of Ports: 1
• Supply Current: 16mA
• Operating Supply Voltage (min): 2.2V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 32
• Word Size: 8b
• Number Of Words: 128K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Switching Characteristics
(Over the Operating Range)
Notes
Document #: 38-05579 Rev. *I
Read Cycle
t
t
t
t
t
t
t
t
t
t
t
Write Cycle
t
t
t
t
t
t
t
t
t
t
13. CE is the logical combination of CE
14. Test Conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns or less (1 V/ns), timing reference levels of V
15. At any given temperature and voltage condition, t
16. t
17. The internal write time of the memory is defined by the overlap of WE, CE = V
RC
AA
OHA
ACE
DOE
LZOE
HZOE
LZCE
HZCE
PU
PD
WC
SCE
AW
HA
SA
PWE
SD
HD
HZWE
LZWE
pulse levels of 0 to V
terminate a write by going INACTIVE. The data input setup and hold timing should be referenced to the edge of the signal that terminates the write.
HZOE
, t
Parameter
HZCE
V
CE
CC
[17]
, and t
HZWE
CC(typ)
transitions are measured when the output enter a high impedance state.
, and output loading of the specified I
[13, 14]
Read cycle time
Address to data valid
Data hold from address change
CE LOW to data valid
OE LOW to data valid
OE LOW to low Z
OE HIGH to high Z
CE LOW to low Z
CE HIGH to high Z
CE LOW to power-up
CE HIGH to power-down
Write cycle time
CE LOW to write end
Address setup to write end
Address hold from write end
Address setup to write start
WE pulse width
Data setup to write end
Data hold from write end
WE LOW to high Z
WE HIGH to low Z
1
and CE
2
. When CE
V
HZCE
t
CC(min)
CDR
Figure 5. Data Retention Waveform
is less than t
[15]
[15]
1
[15]
[15, 16]
[15, 16]
[15, 16]
is LOW and CE
Description
OL
/I
LZCE
OH
as shown in the
DATA RETENTION MODE
, t
2
HZOE
is HIGH, CE is LOW; when CE
IL
is less than t
. All signals must be ACTIVE to initiate a write and any of these signals can
V
DR
> 1.5 V
“AC Test Loads and Waveforms”
LZOE
, and t
[13]
HZWE
1
is HIGH or CE
is less than t
Min
45
10
10
45
35
35
35
25
10
–
–
–
5
–
–
0
–
0
0
0
45 ns (Industrial)
V
CY62128EV30 MoBL
CC(min)
on page 5.
t
LZWE
R
2
is LOW, CE is HIGH.
for any given device.
Max
45
45
22
18
18
45
18
–
–
–
–
–
–
–
–
–
–
–
–
–
–
CC(typ)
Page 6 of 15
/2, input
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
®
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