CY62128EV30LL-45ZXIT Cypress Semiconductor Corp, CY62128EV30LL-45ZXIT Datasheet - Page 8
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CY62128EV30LL-45ZXIT
Manufacturer Part Number
CY62128EV30LL-45ZXIT
Description
CY62128EV30LL-45ZXIT
Manufacturer
Cypress Semiconductor Corp
Specifications of CY62128EV30LL-45ZXIT
Format - Memory
RAM
Memory Type
SRAM
Memory Size
1M (128K x 8)
Speed
45ns
Interface
Parallel
Voltage - Supply
2.2 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Package / Case
32-TSOP I
Density
1Mb
Access Time (max)
45ns
Sync/async
Asynchronous
Architecture
Not Required
Clock Freq (max)
Not RequiredMHz
Operating Supply Voltage (typ)
3V
Address Bus
17b
Package Type
TSOP-I
Operating Temp Range
-40C to 85C
Number Of Ports
1
Supply Current
16mA
Operating Supply Voltage (min)
2.2V
Operating Supply Voltage (max)
3.6V
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
32
Word Size
8b
Number Of Words
128K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
CY62128EV30LL-45ZXIT
Manufacturer:
CRYSTAL
Quantity:
1 408
Part Number:
CY62128EV30LL-45ZXIT
Manufacturer:
CYPRESS/赛普拉斯
Quantity:
20 000
Switching Waveforms
Truth Table
Notes
Document #: 38-05579 Rev. *I
26. CE is the logical combination of CE
27. The internal write time of the memory is defined by the overlap of WE, CE = V
28. Data I/O is high impedance if OE = V
29. If CE
30. During this period, the I/Os are in output state. Do not apply input signals.
31. The ‘X’ (Don’t care) state for the Chip enables in the truth table refer to the logic state (either HIGH or LOW). Intermediate voltage levels on these pins is not permitted.
ADDRESS
ADDRESS
CE
a write by going INACTIVE. The data input setup and hold timing should be referenced to the edge of the signal that terminates the write.
X
DATA I/O
DATA I/O
H
L
L
L
[31]
1
1
goes HIGH or CE
WE
WE
CE
CE
CE
X
H
H
H
L
[31]
2
NOTE 30
2
goes LOW simultaneously with WE HIGH, the output remains in high impedance state.
WE
t
SA
X
X
H
H
L
1
Figure 9. Write Cycle No. 2 CE1 or CE2 controlled
(continued)
and CE
IH
Figure 10. Write Cycle No. 3 WE controlled, OE LOW
.
t
HZWE
OE
2
X
X
X
H
L
. When CE
t
SA
1
is LOW and CE
Inputs/Outputs
t
AW
t
Data out
AW
Data in
High Z
High Z
High Z
t
SCE
t
2
t
WC
WC
t
is HIGH, CE is LOW; when CE
PWE
IL
. All signals must be ACTIVE to initiate a write and any of these signals can terminate
t
PWE
t
DATA VALID
DATA VALID
t
SCE
SD
t
Selected, outputs disabled
SD
Deselect/power-down
Deselect/power-down
Mode
Read
Write
[26, 27, 28, 29]
1
is HIGH or CE
[26, 29]
t
HD
t
t
HA
LZWE
CY62128EV30 MoBL
t
HA
t
HD
2
is LOW, CE is HIGH.
Standby (I
Standby (I
Active (I
Active (I
Active (I
Power
Page 8 of 15
CC
CC
CC
SB
SB
)
)
)
)
)
®
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