CY7C0851AV-133BBI Cypress Semiconductor Corp, CY7C0851AV-133BBI Datasheet - Page 16

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CY7C0851AV-133BBI

Manufacturer Part Number
CY7C0851AV-133BBI
Description
CY7C0851AV-133BBI
Manufacturer
Cypress Semiconductor Corp
Datasheet

Specifications of CY7C0851AV-133BBI

Format - Memory
RAM
Memory Type
SRAM - Dual Port, Synchronous
Memory Size
2M (64K x 36)
Speed
133MHz
Interface
Parallel
Voltage - Supply
3.135 V ~ 3.465 V
Operating Temperature
-40°C ~ 85°C
Package / Case
172-LFBGA
Density
2Mb
Access Time (max)
4.4ns
Sync/async
Synchronous
Architecture
SDR
Clock Freq (max)
133MHz
Operating Supply Voltage (typ)
3.3V
Address Bus
16b
Package Type
TQFP
Operating Temp Range
-40C to 85C
Number Of Ports
2
Supply Current
300mA
Operating Supply Voltage (min)
3.135V
Operating Supply Voltage (max)
3.465V
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
176
Word Size
36b
Number Of Words
64K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CY7C0851AV-133BBI
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
Switching Characteristics
Over the Operating Range (continued)
Document #: 38-06070 Rev. *J
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Notes
OE
OLZ
OHZ
CD2
CA2
CM2
DC
CKHZ
CKLZ
SINT
RINT
SCINT
RCINT
CCS
RS
RSS
RSR
RSF
RSCNTINT
24. This parameter is guaranteed by design, but it is not production tested.
25. Test conditions used are Load 2.
Parameter
Port to Port Delays
Master Reset Timing
[24, 25]
[24, 25]
[24, 25]
[24, 25]
Output enable to data valid
OE to Low Z
OE to High Z
Clock to data valid
Clock to counter address valid
Clock to mask register readback valid
Data output hold after clock HIGH
Clock HIGH to output High Z
Clock HIGH to output Low Z
Clock to INT set time
Clock to INT reset time
Clock to CNTINT set time
Clock to CNTINT reset time
Clock to clock skew
Master reset pulse width
Master reset setup time
Master reset recovery time
Master reset to outputs inactive
Master reset to counter interrupt flag
reset time
Description
CY7C0851V/AV
CY7C0852V/AV
CY7C0850AV
Min
1.0
1.0
0.5
0.5
0.5
0.5
5.2
7.0
6.0
6.0
0
0
0
-167
CY7C0850AV,CY7C0851V/CY7C0851AV
Max
10.0
10.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
6.7
6.7
5.0
5.0
CY7C0851V/AV
CY7C0852V/AV
CY7C0850AV
Min
1.0
1.0
0.5
0.5
0.5
0.5
6.0
7.5
6.0
7.5
0
0
0
Max
10.0
10.0
4.4
4.4
4.4
4.4
4.4
4.4
4.4
7.5
7.5
5.7
5.7
-133
CY7C0852V/CY7C0852AV
CY7C0853V/CY7C0853AV
CY7C0853AV
CY7C0853V
Min
1.0
1.0
0.5
0.5
NA
NA
6.0
7.5
6.0
7.5
0
0
0
Max
10.0
4.7
4.7
4.7
NA
NA
4.7
4.7
7.5
7.5
NA
NA
NA
CY7C0853AV
10.0
10.0
CY7C0853V
Min
1.0
1.0
0.5
0.5
NA
NA
8.0
8.5
0
0
0
-100
Page 16 of 36
Max
10.0
5.0
5.0
5.0
NA
NA
5.0
5.0
NA
NA
NA
10
10
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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