CY7C0851AV-133BBI Cypress Semiconductor Corp, CY7C0851AV-133BBI Datasheet - Page 18

• Manufacturer Part Number: CY7C0851AV-133BBI
• Description: CY7C0851AV-133BBI
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C0851AV-133BBI

• Format - Memory: RAM
• Memory Type: SRAM - Dual Port, Synchronous
• Memory Size: 2M (64K x 36)
• Speed: 133MHz
• Interface: Parallel
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 172-LFBGA
• Density: 2Mb
• Access Time (max): 4.4ns
• Sync/async: Synchronous
• Architecture: SDR
• Clock Freq (max): 133MHz
• Operating Supply Voltage (typ): 3.3V
• Address Bus: 16b
• Package Type: TQFP
• Operating Temp Range: -40C to 85C
• Number Of Ports: 2
• Supply Current: 300mA
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.465V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 176
• Word Size: 36b
• Number Of Words: 64K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Switching Waveforms
Notes
Document #: 38-06070 Rev. *J
26. CE is internal signal. CE = LOW if CE
27. OE is asynchronously controlled; all other inputs (excluding MRST and JTAG) are synchronous to the rising clock edge.
28. ADS = CNTEN = LOW, and MRST = CNTRST = CNT/MSK = HIGH.
29. The output is disabled (high-impedance state) by CE = V
30. Addresses do not have to be accessed sequentially since ADS = CNTEN = V
can be deasserted after that. Data is out after the following CLK edge and is three-stated after the next CLK edge.
Numbers are for reference only.
MRST
ALL
ADDRESS/
DATA
LINES
ALL
OTHER
INPUTS
TMS
CNTINT
INT
TDO
ADDRESS
DATA
B0–B3
R/W
CLK
OUT
OE
CE
t
t
t
RSF
t
t
SB
SW
SA
SC
A
n
t
RS
t
t
t
t
HB
HW
HA
t
HC
0
CH2
1 Latency
= LOW and CE
t
INACTIVE
RSS
t
CYC2
t
RSR
t
CKLZ
t
CL2
1
Figure 9. Read Cycle
= HIGH. For a single Read operation, CE only needs to be asserted once at the rising edge of the CLK and
IH
A
following the next rising edge of the clock.
n+1
Figure 8. Master Reset
ACTIVE
t
CD2
IL
with CNT/MSK = V
CY7C0850AV,CY7C0851V/CY7C0851AV
[26, 27, 28, 29, 30]
Q
A
n
n+2
IH
constantly loads the address on the rising edge of the CLK.
t
DC
CY7C0852V/CY7C0852AV
CY7C0853V/CY7C0853AV
Q
t
SC
n+1
t
OHZ
A
n+3
t
OLZ
t
HC
t
OE
Page 18 of 36
Q
n+2
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