CY7C0851AV-133BBI Cypress Semiconductor Corp, CY7C0851AV-133BBI Datasheet - Page 21

• Manufacturer Part Number: CY7C0851AV-133BBI
• Description: CY7C0851AV-133BBI
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C0851AV-133BBI

• Format - Memory: RAM
• Memory Type: SRAM - Dual Port, Synchronous
• Memory Size: 2M (64K x 36)
• Speed: 133MHz
• Interface: Parallel
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 172-LFBGA
• Density: 2Mb
• Access Time (max): 4.4ns
• Sync/async: Synchronous
• Architecture: SDR
• Clock Freq (max): 133MHz
• Operating Supply Voltage (typ): 3.3V
• Address Bus: 16b
• Package Type: TQFP
• Operating Temp Range: -40C to 85C
• Number Of Ports: 2
• Supply Current: 300mA
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.465V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 176
• Word Size: 36b
• Number Of Words: 64K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Switching Waveforms
Document #: 38-06070 Rev. *J
Note
41. CE
INTERNAL
(labelled as no operation). One clock cycle is required to three-state the I/O for the Write operation on the next rising edge of CLK.
ADDRESS
ADDRESS
CNTEN
0
DATA
= B0 – B3 = R/W = LOW; CE
ADS
DATA
ADDRESS
CLK
DATA
IN
OUT
CLK
R/W
OE
CE
t
t
SCN
t
t
SAD
SA
SD
IN
WRITE EXTERNAL
D
A
DISABLED
n
n
ADDRESS
t
CH2
1
= CNTRST = MRST = CNT/MSK = HIGH. When R/W first switches low, since OE = LOW, the Write operation cannot be completed
t
CYC2
t
t
t
SA
t
HAD
HCN
t
(continued)
t
HA
HD
SC
t
CL2
t
CL2
A
t
Figure 15. Disabled to Read-to-Read to Read-to-Write
SW
n
Figure 14. Write with Address Counter Advance
t
CYC2
A
n
t
D
HW
n+1
t
CH2
READ
WRITE WITH
t
t
HC
COUNTER
HA
A
n+1
D
t
n+1
CD2
WRITE COUNTER
A
n+1
READ
HOLD
CY7C0850AV,CY7C0851V/CY7C0851AV
Q
n
A
n+2
D
n+2
READ
Q
n+1
t
SA
t
SW
A
CY7C0852V/CY7C0852AV
CY7C0853V/CY7C0853AV
n+2
t
[41]
SD
WRITE WITH COUNTER
A
D
n+3
D
n+3
n+3
t
HD
WRITE
t
t
HA
HW
A
n+3
D
A
n+4
n+4
READ
A
Page 21 of 36
n+4
Q
n+2
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