CY7C1381D-133AXC Cypress Semiconductor Corp, CY7C1381D-133AXC Datasheet

IC,SYNC SRAM,512KX36,CMOS,QFP,100PIN,PLASTIC

CY7C1381D-133AXC

Manufacturer Part Number

CY7C1381D-133AXC

Description

IC,SYNC SRAM,512KX36,CMOS,QFP,100PIN,PLASTIC

Manufacturer

Cypress Semiconductor Corp

Datasheets

1.CY7C1381D-133AXC.pdf (29 pages)

2.CY7C1381D-133AXC.pdf (29 pages)

3.CY7C1381D-133AXC.pdf (29 pages)

4.CY7C1381F-133BGCT.pdf (17 pages)

Specifications of CY7C1381D-133AXC

Format - Memory

RAM

Memory Type

SRAM - Synchronous

Memory Size

18M (512K x 36)

Speed

133MHz

Interface

Parallel

Voltage - Supply

3.135 V ~ 3.6 V

Operating Temperature

0°C ~ 70°C

Package / Case

100-LQFP

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Available stocks

Company

Part Number

Manufacturer

Quantity

Price

Company:

Bonase Electronics (HK) Co., Limited

Part Number:

CY7C1381D-133AXC

Manufacturer:

CYPRESS

Quantity:

101

Company:

BOSTOCK HK LIMITED

Part Number:

CY7C1381D-133AXC

Manufacturer:

Cypress Semiconductor Corp

Quantity:

10 000

Company:

BOSTOCK HK LIMITED

Part Number:

CY7C1381D-133AXCT

Manufacturer:

Cypress Semiconductor Corp

Quantity:

10 000

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Download datasheet (470Kb)

Cypress Semiconductor Corporation

Document #: 38-05544 Rev. *A

Features

Selection Guide

Maximum Access Time

Maximum Operating Current

Maximum CMOS Standby Current

Notes:

• Supports 133-MHz bus operations

• 512K × 36/1M × 18 common I/O

• 3.3V –5% and +10% core power supply (V

• 2.5V or 3.3V I/O supply (V

• Fast clock-to-output time

• Provide high-performance 2-1-1-1 access rate

• User-selectable burst counter supporting Intel

• Separate processor and controller address strobes

• Synchronous self-timed write

• Asynchronous output enable

• Offered in JEDEC-standard lead-free 100-pin TQFP

• JTAG boundary scan for BGA and fBGA packages

• “ZZ” Sleep Mode option

1. For best–practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.

2. CE

— 6.5 ns (133-MHz version)

— 8.5 ns (100-MHz version)

Pentium

,119-ball BGA and 165-ball fBGA packages

are for TQFP and 165 fBGA package only. 119 BGA is offered only in 1 Chip Enable.



interleaved or linear burst sequences

18-Mbit (512K x 36/1M x 18) Flow-Through SRAM

DDQ

)

•

3901 North First Street

)

PRELIMINARY



Functional Description

The CY7C1381D/CY7C1383D is a 3.3V, 512K x 36 and 1 Mbit

x 18 Synchronous Flow-through SRAMs, respectively

designed to interface with high-speed microprocessors with

minimum glue logic. Maximum access delay from clock rise is

6.5 ns (133-MHz version). A 2-bit on-chip counter captures the

first address in a burst and increments the address automati-

cally for the rest of the burst access. All synchronous inputs

are gated by registers controlled by a positive-edge-triggered

Clock Input (CLK). The synchronous inputs include all

addresses, all data inputs, address-pipelining Chip Enable

( CE

Control inputs ( ADSC , ADSP , and ADV ), Write Enables ( BW

and BWE ), and Global Write ( GW ). Asynchronous inputs

include the Output Enable ( OE ) and the ZZ pin .

The CY7C1381D/CY7C1383D allows either interleaved or

linear burst sequences, selected by the MODE input pin. A

HIGH selects an interleaved burst sequence, while a LOW

selects a linear burst sequence. Burst accesses can be

initiated with the Processor Address Strobe (ADSP) or the

cache Controller Address Strobe (ADSC) inputs. Address

advancement is controlled by the Address Advancement

(ADV) input.

Addresses and chip enables are registered at rising edge of

clock when either Address Strobe Processor ( ADSP ) or

Address Strobe Controller ( ADSC ) are active. Subsequent

burst addresses can be internally generated as controlled by

the Advance pin ( ADV ).

The CY7C1381D/CY7C1383D operates from a +3.3V core

power supply while all outputs may operate with either a +2.5

or +3.3V supply. All inputs and outputs are JEDEC-standard

JESD8-5-compatible.

133 MHz

), depth-expansion Chip Enables (CE

210

6.5

•

San Jose

CA 95134

100 MHz

[1]

175

8.5

Revised November 2, 2004

•

CY7C1381D

CY7C1383D

and CE

408-943-2600

Unit

[2]

), Burst

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