CY7C1423AV18-250BZC Cypress Semiconductor Corp, CY7C1423AV18-250BZC Datasheet

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... K and K if C/C are not provided. Each address location is associated with two 8-bit words in the case of CY7C1422AV18, two 9-bit words in the case of CY7C1429AV18, two 18-bit words in the case of CY7C1423AV18, and two 36-bit words in the case of CY7C1424AV18 that burst sequentially into ) DD or out of the device ...

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... Address A (20:0) Register K CLK K Gen. DOFF R/W V REF Control Logic LD BWS [0] Document Number: 38-05617 Rev. *I CY7C1422AV18, CY7C1429AV18 CY7C1423AV18, CY7C1424AV18 Write Write Data Reg Data Reg Control Logic Read Data Reg Reg. Reg. 8 Reg. Write Write Data Reg Data Reg Control Logic Read Data Reg ...

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... Logic Block Diagram (CY7C1423AV18 [17:0] 20 Address A (19:0) Register K CLK K Gen. DOFF R/W V REF Control Logic LD BWS [1:0] Logic Block Diagram (CY7C1424AV18 [35:0] 19 Address A (18:0) Register K CLK K Gen. DOFF R/W V REF Control Logic LD BWS [3:0] Document Number: 38-05617 Rev. *I CY7C1422AV18, CY7C1429AV18 CY7C1423AV18, CY7C1424AV18 ...

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... TAP Instruction Set ................................................... 14 TAP Controller State Diagram ....................................... 16 TAP Controller Block Diagram ...................................... 17 TAP Electrical Characteristics ...................................... 17 Document Number: 38-05617 Rev. *I CY7C1422AV18, CY7C1429AV18 CY7C1423AV18, CY7C1424AV18 TAP AC Switching Characteristics ............................... 18 TAP Timing and Test Conditions .................................. 18 Identification Register Definitions ................................ 19 Scan Register Sizes ....................................................... 19 Instruction Codes ........................................................... 19 Boundary Scan Order .................................................... 20 Power Up Sequence in DDR-II SRAM ...

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... Selection Guide Description Maximum Operating Frequency Maximum Operating Current ×8 ×9 ×18 ×36 Document Number: 38-05617 Rev. *I CY7C1422AV18, CY7C1429AV18 CY7C1423AV18, CY7C1424AV18 300 MHz 278 MHz 250 MHz 300 278 250 825 775 700 845 775 700 880 815 740 980 890 ...

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... Pin Configuration The pin configuration for CY7C1422AV18, CY7C1429AV18, CY7C1423AV18, and CY7C1424AV18 follow NC/72M DOFF V V REF DDQ TDO TCK NC/72M DOFF V V REF DDQ TDO TCK A Note 1. NC/72M, NC/144M, and NC/288M are not connected to the die and can be tied to any voltage level. ...

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... Pin Configuration (continued) The pin configuration for CY7C1422AV18, CY7C1429AV18, CY7C1423AV18, and CY7C1424AV18 follow NC/144M D10 D NC D11 Q10 Q11 F NC Q12 D12 G NC D13 Q13 H DOFF V V REF DDQ D14 Q14 L NC Q15 D15 D16 N NC D17 Q16 Q17 R TDO TCK ...

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... Synchronous arrays each for CY7C1422AV18 arrays each for CY7C1429AV18 arrays each 18) for CY7C1423AV18 and arrays each of 512K x 36) for CY7C1424AV18. Therefore, only 21 address inputs are needed to access the entire memory array of CY7C1422AV18 and CY7C1429AV18, 20 address inputs for CY7C1423AV18 and 19 address inputs for CY7C1424AV18 ...

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... Ground for the Device Power Supply Power Supply Inputs for the Outputs of the Device. DDQ Document Number: 38-05617 Rev. *I CY7C1422AV18, CY7C1429AV18 CY7C1423AV18, CY7C1424AV18 Pin Description Switching Characteristics on page Switching Characteristics on page output impedance are set to 0.2 x RQ, where resistor connected [x:0] 25. ...

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... This feature can be used to simplify read/modify/write operations to a byte write operation. Single Clock Mode The CY7C1423AV18 can be used with a single clock that controls both the input and output registers. In this mode the device recognizes only a single pair of input clocks (K and K) that ) inputs pass through control both the input and output registers ...

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... 50Ohms Document Number: 38-05617 Rev. *I CY7C1422AV18, CY7C1429AV18 CY7C1423AV18, CY7C1424AV18 minimum of 30 ns. However not necessary to reset the DLL to lock it to the desired frequency. The DLL automatically locks 1024 clock cycles after a stable clock is presented. The DLL may be disabled by applying ground to the DOFF pin. For information refer to the application note QDRII/DDRII/QDRII+/DDRII+ ...

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... Truth Table The truth table for CY7C1422AV18, CY7C1429AV18, CY7C1423AV18, and CY7C1424AV18 follows. Operation Write Cycle: Load address; wait one cycle; input write data on consecutive K and K rising edges. Read Cycle: Load address; wait one and a half cycle; read data on consecutive C and C rising edges. ...

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... X = “Don't Care,” Logic HIGH Logic LOW, 10. Is based on a write cycle that was initiated in accordance with the different portions of a write cycle, as long as the setup and hold requirements are achieved. Document Number: 38-05617 Rev. *I CY7C1422AV18, CY7C1429AV18 CY7C1423AV18, CY7C1424AV18 [9, 10] Comments [9, 10] K – ...

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... TDI pin on the rising edge of TCK. Data is output on the TDO pin on the falling edge of TCK. Document Number: 38-05617 Rev. *I CY7C1422AV18, CY7C1429AV18 CY7C1423AV18, CY7C1424AV18 Instruction Register Three-bit instructions can be serially loaded into the instruction register. This register is loaded when it is placed between the TDI and TDO pins, as shown in page 17 ...

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... Document Number: 38-05617 Rev. *I CY7C1422AV18, CY7C1429AV18 CY7C1423AV18, CY7C1424AV18 BYPASS When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between the TDI and TDO pins ...

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... The state diagram for the TAP controller follows. TEST-LOGIC 1 RESET 0 1 TEST-LOGIC/ 0 IDLE Note 11. The 0/1 next to each state represents the value at TMS at the rising edge of TCK. Document Number: 38-05617 Rev. *I CY7C1422AV18, CY7C1429AV18 CY7C1423AV18, CY7C1424AV18 [11] 1 SELECT DR-SCAN 0 1 CAPTURE- SHIFT- ...

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... These characteristics pertain to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in the 13. Overshoot: V (AC) < 0.85 V (Pulse width less than t IH DDQ 14. All Voltage referenced to Ground. Document Number: 38-05617 Rev. *I CY7C1422AV18, CY7C1429AV18 CY7C1423AV18, CY7C1424AV18 0 Bypass Register Instruction Register ...

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... CS CH 16. Test conditions are specified using the load in TAP AC Test Conditions. t Document Number: 38-05617 Rev. *I CY7C1422AV18, CY7C1429AV18 CY7C1423AV18, CY7C1424AV18 Description [16] Figure 2. TAP Timing and Test Conditions 0.9V 1.8V 50 ...

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... Do Not Use: This instruction is reserved for future use. BYPASS 111 Places the bypass register between TDI and TDO. This operation does not affect SRAM operation. Document Number: 38-05617 Rev. *I CY7C1422AV18, CY7C1429AV18 CY7C1423AV18, CY7C1424AV18 Value CY7C1429AV18 CY7C1423AV18 000 000 11010100010001111 11010100010010111 ...

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... Document Number: 38-05617 Rev. *I CY7C1422AV18, CY7C1429AV18 CY7C1423AV18, CY7C1424AV18 Bump ID Bit # Bump ID 10G 11F 58 5A 11G 10F 61 4B 11E 62 3A 10E 63 2A 10D 10C 66 3B 11D ...

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... DDQ DOFF Document Number: 38-05617 Rev. *I CY7C1422AV18, CY7C1429AV18 CY7C1423AV18, CY7C1424AV18 DLL Constraints DLL uses K clock as its synchronizing input. The input must ■ have low phase jitter, which is specified as t The DLL functions at frequencies down to 120 MHz. ■ If the input clock is unstable and the DLL is enabled, then the ■ ...

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... whichever is larger, V REF DDQ 23. The operation current is calculated with 50% read cycle and 50% write cycle. Document Number: 38-05617 Rev. *I CY7C1422AV18, CY7C1429AV18 CY7C1423AV18, CY7C1424AV18 Current into Outputs (LOW)......................................... 20 mA Static Discharge Voltage (MIL-STD-883, M. 3015). > 2001 V Latch-up Current.................................................... > 200 mA Operating Range Range Commercial ...

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... IH V Input LOW Voltage IL Notes 24. The operation current is calculated with 50% read cycle and 50% write cycle. 25. Overshoot: V (AC) < 0.85 V (Pulse width less than t IH DDQ Document Number: 38-05617 Rev. *I CY7C1422AV18, CY7C1429AV18 CY7C1423AV18, CY7C1424AV18 Test Conditions V = Max, 200 MHz (× mA, OUT (× 1/t ...

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... Note 26. Unless otherwise noted, test conditions are based on signal transition time of 2 V/ns, timing reference levels of 0.75 V, Vref = 0. 250 , V pulse levels of 0. 1.25 V, and output loading of the specified I Document Number: 38-05617 Rev. *I CY7C1422AV18, CY7C1429AV18 CY7C1423AV18, CY7C1424AV18 Test Conditions = 25  MHz 1 ...

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... This part has a voltage regulator internally; t POWER initiated. 30. For D2 data signal on CY7C1429AV18 device, t Document Number: 38-05617 Rev. *I CY7C1422AV18, CY7C1429AV18 CY7C1423AV18, CY7C1424AV18 300 MHz 278 MHz Min Max Min Max Min Max Min Max Min Max [29] 1 – ...

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... CHZ CLZ 32. At any voltage and temperature t is less than t CHZ Document Number: 38-05617 Rev. *I CY7C1422AV18, CY7C1429AV18 CY7C1423AV18, CY7C1424AV18 300 MHz 278 MHz Min Max Min Max Min Max Min Max Min Max – 0.45 – 0.45 – ...

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... Outputs are disabled (high Z) one clock cycle after a NOP. 35. In this example, if address A4 = A3, then data Q40 = D30 and Q41 = D31. Write data is forwarded immediately as read results. This note applies to the whole diagram. Document Number: 38-05617 Rev. *I CY7C1422AV18, CY7C1429AV18 CY7C1423AV18, CY7C1424AV18 WRITE READ WRITE ...

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... For a complete listing of all options, visit the Cypress website at to the product summary page at http://www.cypress.com/products worldwide network of offices, solution centers, manufacturer's representatives and distributors. To find the office closest to you, visit http://www.cypress.com/go/datasheet/offices. Speed (MHz) Ordering Code 250 CY7C1423AV18-250BZC 267 CY7C1423AV18-267BZC Ordering Code Definitions 14XX A V18 - XXX Document Number: 38-05617 Rev ...

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... Package Diagram Figure 6. 165-ball FBGA (15 × 17 × 1.4 mm), 51-85195 Document Number: 38-05617 Rev. *I CY7C1422AV18, CY7C1429AV18 CY7C1423AV18, CY7C1424AV18 51-85195 *B Page [+] Feedback ...

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... Document Conventions Units of Measure Symbol Unit of Measure ns nano seconds V Volts  ohms µA micro Amperes mA milli Amperes mm milli meter ms milli seconds MHz Mega Hertz pF pico Farad °C degree Celcius W Watts Document Number: 38-05617 Rev. *I CY7C1422AV18, CY7C1429AV18 CY7C1423AV18, CY7C1424AV18 Page [+] Feedback ...

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... Document History Page Document Title: CY7C1422AV18/CY7C1429AV18/CY7C1423AV18/CY7C1424AV18, 36-Mbit DDR-II SIO SRAM 2-Word Burst Architecture Document Number: 38-05617 Submission ORIG. OF REV. ECN NO. DATE CHANGE ** 247331 See ECN SYT *A 326519 See ECN SYT *B 413953 See ECN NXR *C 468029 See ECN NXR Document Number: 38-05617 Rev. *I ...

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... Document History Page Document Title: CY7C1422AV18/CY7C1429AV18/CY7C1423AV18/CY7C1424AV18, 36-Mbit DDR-II SIO SRAM 2-Word Burst Architecture Document Number: 38-05617 *D 2511746 See ECN VKN/AESA Updated Logic Block diagram *E 2898663 03/24/2010 NJY *F 2906713 04/07/2010 NJY *G 3068494 10/21/10 HMLA *H 3088678 11/27/2010 NJY *I 3101284 12/03/2010 NJY Document Number: 38-05617 Rev. *I ...

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... DDR RAMs and QDR RAMs comprise a new family of products developed by Cypress, Hitachi, IDT, Micron, NEC, and Samsung. All products and company names mentioned in this document may be the trademarks of their respective holders. CY7C1422AV18, CY7C1429AV18 CY7C1423AV18, CY7C1424AV18 cypress.com/go/plc Revised December 3, 2010 PSoC Solutions psoc ...