CY7C4221-15AXC Cypress Semiconductor Corp, CY7C4221-15AXC Datasheet - Page 11

IC,FIFO,1KX9,SYNCHRONOUS,CMOS,TQFP,32PIN,PLASTIC

CY7C4221-15AXC

Manufacturer Part Number
CY7C4221-15AXC
Description
IC,FIFO,1KX9,SYNCHRONOUS,CMOS,TQFP,32PIN,PLASTIC
Manufacturer
Cypress Semiconductor Corp
Series
CY7Cr
Datasheets

Specifications of CY7C4221-15AXC

Function
Synchronous
Memory Size
9K (1K x 9)
Data Rate
100MHz
Access Time
10ns
Voltage - Supply
3.3V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
32-TQFP
Configuration
Dual
Density
8Kb
Access Time (max)
10ns
Word Size
9b
Organization
1Kx9
Sync/async
Synchronous
Expandable
Yes
Bus Direction
Uni-Directional
Package Type
TQFP
Clock Freq (max)
66.7MHz
Operating Supply Voltage (typ)
5V
Operating Supply Voltage (min)
4.5V
Operating Supply Voltage (max)
5.5V
Supply Current
35mA
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
32
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CY7C4221-15AXC
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
Part Number:
CY7C4221-15AXCT
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
Switching Waveforms
Document #: 38-06016 Rev. *F
REN1,REN2
Notes
14. t
15. t
(if applicable)
REN1,REN2
the rising edge of RCLK and the rising edge of WCLK is less than t
the rising edge of WCLK and the rising edge of RCLK is less than t
SKEW1
SKEW1
WEN2
Q
D
WCLK
WEN1
WEN1
WEN2
WCLK
RCLK
0
RCLK
0
–Q
–D
OE
FF
EF
is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF goes HIGH during the current clock cycle. If the time between
is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF goes HIGH during the current clock cycle. It the time between
8
8
t
ENS
t
OLZ
t
SKEW1
t
ENH
[14]
t
t
CLKH
CLKH
t
t
t
WFF
A
REF
t
OE
t
t
CLK
CKL
t
Figure 5. Write Cycle Timing
Figure 6. Read Cycle Timing
SKEW1
NO OPERATION
SKEW1
SKEW1
[15]
t
DS
t
t
CLKL
CLKL
, then FF may not change state until the next WCLK rising edge.
, then EF may not change state until the next RCLK rising edge.
t
ENS
t
Valid Data
DH
t
ENH
t
CY7C4421 / 4201 / 4211 / 4221
REF
t
WFF
t
OHZ
CY7C4231 / 4241 / 4251
No Operation
No Operation
Page 11 of 23
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