CY7C4221-15AXC Cypress Semiconductor Corp, CY7C4221-15AXC Datasheet - Page 4

• Manufacturer Part Number: CY7C4221-15AXC
• Description: IC,FIFO,1KX9,SYNCHRONOUS,CMOS,TQFP,32PIN,PLASTIC
• Manufacturer: Cypress Semiconductor Corp
• Series: CY7Cr

Specifications of CY7C4221-15AXC

• Function: Synchronous
• Memory Size: 9K (1K x 9)
• Data Rate: 100MHz
• Access Time: 10ns
• Voltage - Supply: 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-TQFP
• Configuration: Dual
• Density: 8Kb
• Access Time (max): 10ns
• Word Size: 9b
• Organization: 1Kx9
• Sync/async: Synchronous
• Expandable: Yes
• Bus Direction: Uni-Directional
• Package Type: TQFP
• Clock Freq (max): 66.7MHz
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Supply Current: 35mA
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 32
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Pin Configuration
Table 1. Pin Definitions
Document #: 38-06016 Rev. *F
D
Q
WEN1
WEN2/LD Dual
Mode Pin
REN1, REN2
WCLK
RCLK
EF
FF
PAE
PAF
RS
OE
0–8
0–8
Pin
Data Inputs
Data Outputs
Write Enable 1
Write Enable 2
Load
Read Enable
Inputs
Write Clock
Read Clock
Empty Flag
Full Flag
Programmable
Almost Empty
Programmable
Almost Full
Reset
Output Enable
Name
REN1
RCLK
REN2
GND
PAE
PAF
OE
D
D
1
0
5
6
7
8
9
10
11
12
13
Top View
4 3 2 1
14151617 181920
I/O
PLCC
O
O
O
O
O
I
I
I
I
I
I
I
I
I
Data inputs for 9-bit bus.
Data outputs for 9-bit bus.
The only write enable to have programmable flags when device is configured. Data is
written on a LOW-to-HIGH transition of WCLK when WEN1 is asserted and FF is HIGH.
If the FIFO is configured to have two write enables, data is written on a LOW-to-HIGH
transition of WCLK when WEN1 is LOW and WEN2/LD and FF are HIGH.
If HIGH at reset, this pin operates as a second write enable. If LOW at reset, this pin
operates as a control to write or read the programmable flag offsets. WEN1 must be
LOW and WEN2 must be HIGH to write data into the FIFO. Data is not written into the
FIFO if the FF is LOW. If the FIFO is configured to have programmable flags, WEN2/LD
is held LOW to write or read the programmable flag offsets.
Enables device for read operation.
The rising edge clocks data into the FIFO when WEN1 is LOW, WEN2/LD is HIGH, and
the FIFO is not Full. When LD is asserted, WCLK writes data into the programmable
flag-offset register.
The rising edge clocks data out of the FIFO when REN1 and REN2 are LOW and the
FIFO is not Empty. When WEN2/LD is LOW, RCLK reads data out of the programmable
flag-offset register.
When EF is LOW, the FIFO is empty. EF is synchronized to RCLK.
When FF is LOW, the FIFO is full. FF is synchronized to WCLK.
When PAE is LOW, the FIFO is almost empty based on the almost empty offset value
programmed into the FIFO.
When PAF is LOW, the FIFO is almost full based on the almost full offset value
programmed into the FIFO.
Resets device to empty condition. A reset is required before an initial read or write
operation after power up.
When OE is LOW, the FIFO’s data outputs drive the bus to which they are connected.
If OE is HIGH, the FIFO’s outputs are in High-Z (high-impedance) state.
32
3130
29
28
27
26
25
24
23
22
21
RS
WEN1
WCLK
WEN2/LD
V
Q
Q
Q
Q
Figure 1. Pin Diagram
CC
8
7
6
5
REN1
RCLK
REN2
GND
PAE
PAF
D
D
1
0
1
2
3
4
5
6
7
8
32
9 10 11 12 13
CY7C4421 / 4201 / 4211 / 4221
Description
31 30
Top View
TQFP
29 28 27
14 15 16
CY7C4231 / 4241 / 4251
26
25
24
23
22
21
20
19
18
17
WEN1
WCLK
WEN2/LD
V
Q
Q
Q
Q
CC
8
7
6
5
Page 4 of 23
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