CY7C4221-15AXC Cypress Semiconductor Corp, CY7C4221-15AXC Datasheet - Page 8

• Manufacturer Part Number: CY7C4221-15AXC
• Description: IC,FIFO,1KX9,SYNCHRONOUS,CMOS,TQFP,32PIN,PLASTIC
• Manufacturer: Cypress Semiconductor Corp
• Series: CY7Cr

Specifications of CY7C4221-15AXC

• Function: Synchronous
• Memory Size: 9K (1K x 9)
• Data Rate: 100MHz
• Access Time: 10ns
• Voltage - Supply: 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-TQFP
• Configuration: Dual
• Density: 8Kb
• Access Time (max): 10ns
• Word Size: 9b
• Organization: 1Kx9
• Sync/async: Synchronous
• Expandable: Yes
• Bus Direction: Uni-Directional
• Package Type: TQFP
• Clock Freq (max): 66.7MHz
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Supply Current: 35mA
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 32
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Width Expansion Configuration
Word width may be increased by connecting the corresponding
input controls signals of multiple devices. A composite flag
should be created for each of the end-point status flags (EF and
FF). The partial status flags (PAE and PAF) can be detected from
any one device.
using two CY7C42X1s. Any word width can be attained by
adding additional CY7C42X1s.
When the CY7C42X1 is in a Width Expansion Configuration, the
Read Enable (REN2) control input can be grounded (See
Figure
(WEN2/LD) pin is set to LOW at Reset so that the pin operates
as a control to load and read the programmable flag offsets.
Document #: 38-06016 Rev. *F
Figure 3. Block Diagram of 64 x 9, 256 x 9, 512 x 9, 1024 x 9, 2048 x 9, 4096 x 9, 8192 x 9 Synchronous FIFO Memory Used
Write
Programmable
Write
Data In (D)
Write
3). In this configuration, the Write Enable 2/Load
Full Flag (FF) # 1
Full Flag (FF) # 2
Enable 1 (WEN1)
Enable 2/LOAD
Clock
Figure 3
(WEN2/LD)
18
(WCLK)
(PAF)
demonstrates a 18-bit word width by
9
Read Enable 2 (REN2)
FF
Reset (RS)
CY7C42X1
in a Width Expansion Configuration
EF
9
9
Flag Operation
The CY7C42X1 devices provide four flag pins to indicate the
condition of the FIFO contents. Empty, Full, PAE, and PAF are
synchronous.
Full Flag
The Full Flag (FF) goes LOW when device is full. Write
operations are inhibited whenever FF is LOW regardless of the
state of WEN1 and WEN2/LD. FF is synchronized to WCLK - it
is exclusively updated by each rising edge of WCLK.
Empty Flag
The Empty Flag (EF) goes LOW when the device is empty. Read
operations are inhibited whenever EF is LOW, regardless of the
state of REN1 and REN2. EF is synchronized to RCLK - it is
exclusively updated by each rising edge of RCLK.
Read Enable 2 (REN2)
FF
Reset (RS)
CY7C42X1
CY7C4421 / 4201 / 4211 / 4221
EF
Empty
Empty Flag (EF) #2
CY7C4231 / 4241 / 4251
Read Clock
Read Enable 1 (REN1)
Output
Programmable
9
Data Out (Q)
Flag (EF) #1
Enable (OE)
(RCLK)
(PAE)
18
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