CY8C3665AXI-010 Cypress Semiconductor Corp, CY8C3665AXI-010 Datasheet - Page 45

• Manufacturer Part Number: CY8C3665AXI-010
• Description: PSOC3
• Manufacturer: Cypress Semiconductor Corp
• Series: PSOC™ 3 CY8C36xxr

Specifications of CY8C3665AXI-010

• Package / Case: *
• Voltage - Supply (vcc/vdd): 1.71 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 67MHz
• Number Of I /o: 62
• Eeprom Size: 1K x 8
• Core Processor: 8051
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Program Memory Size: 32KB (32K x 8)
• Data Converters: A/D 2x12b, D/A 4x8b
• Oscillator Type: Internal
• Peripherals: CapSense, DMA, POR, PWM, WDT
• Connectivity: EBI/EMI, I²C, LIN, SPI, UART/USART
• Core Size: 8-Bit
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Technology: CMOS
• Processing Unit: Microcontroller
• Operating Supply Voltage (min): 1.8V
• Operating Supply Voltage (typ): 2.5/3.3/5V
• Operating Supply Voltage (max): 5.5V
• Package Type: TQFP
• Screening Level: Industrial
• Pin Count: 100
• Mounting: Surface Mount
• Rad Hardened: No
• Processor Series: CY8C36
• Core: 8051
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, SPI, UART, USB
• Maximum Clock Frequency: 67 MHz
• Number Of Programmable I/os: 28 to 72
• Number Of Timers: 4
• Operating Supply Voltage: 0.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Controller Family/series: (8051) PSOC 3
• No. Of I/o's: 62
• Eeprom Memory Size: 1KB
• Ram Memory Size: 4KB
• Cpu Speed: 67MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

7.7 Timers, Counters, and PWMs
The Timer/Counter/PWM peripheral is a 16-bit dedicated
peripheral providing three of the most common embedded
peripheral features. As almost all embedded systems use some
combination of timers, counters, and PWMs. Four of them have
been included on this PSoC device family. Additional and more
advanced functionality timers, counters, and PWMs can also be
instantiated in Universal Digital Blocks (UDBs) as required.
PSoC Creator allows you to choose the timer, counter, and PWM
features that they require. The tool set utilizes the most optimal
resources available.
The Timer/Counter/PWM peripheral can select from multiple
clock sources, with input and output signals connected through
the DSI routing. DSI routing allows input and output connections
to any device pin and any internal digital signal accessible
through the DSI. Each of the four instances has a compare
output, terminal count output (optional complementary compare
output), and programmable interrupt request line. The
Timer/Counter/PWMs are configurable as free running, one shot,
or Enable input controlled. The peripheral has timer reset and
capture inputs, and a kill input for control of the comparator
outputs. The peripheral supports full 16-bit capture.
Timer/Counter/PWM features include:
Figure 7-21. Timer/Counter/PWM
Document Number: 001-53413 Rev. *J
Clock
Reset
Enable
Capture
Kill
16-bit Timer/Counter/PWM (down count only)
Selectable clock source
PWM comparator (configurable for LT, LTE, EQ, GTE, GT)
Period reload on start, reset, and terminal count
Interrupt on terminal count, compare true, or capture
Dynamic counter reads
Timer capture mode
Count while enable signal is asserted mode
Free run mode
One Shot mode (stop at end of period)
Complementary PWM outputs with deadband
PWM output kill
Timer / Counter /
PWM 16-bit
IRQ
TC / Compare!
Compare
PRELIMINARY
7.8 I
The I
designed to interface the PSoC device with a two wire I
communication bus. The bus is compliant with Philips ‘The I
Specification’ version 2.1. Additional I
instantiated using Universal Digital Blocks (UDBs) in PSoC
Creator, as required.
To eliminate the need for excessive CPU intervention and
overhead, I
and generation of framing bits. I
or multimaster (Slave and Master). In slave mode, the unit
always listens for a start condition to begin sending or receiving
data. Master mode supplies the ability to generate the Start and
Stop conditions and initiate transactions. Multimaster mode
provides clock synchronization and arbitration to allow multiple
masters on the same bus. If Master mode is enabled and Slave
mode is not enabled, the block does not generate interrupts on
externally generated Start conditions. I
DSI routing and allows direct connections to any GPIO or SIO
pins.
I
CPU intervention. Additionally the device can wake from
low-power modes on a 7-bit hardware address match. If wakeup
functionality is required, I
two special sets of SIO pins.
I
7.9 Digital Filter Block
Some devices in the CY8C36 family of devices have a dedicated
HW accelerator block used for digital filtering. The DFB has a
dedicated multiplier and accumulator that calculates a 24-bit by
24-bit multiply accumulate in one system clock cycle. This
enables the mapping of a direct form FIR filter that approaches
a computation rate of one FIR tap for each clock cycle. The MCU
can implement any of the functions performed by this block, but
at a slower rate that consumes MCU bandwidth.
The PSoC Creator interface provides a wizard to implement FIR
and IIR digital filters with coefficients for LPF, BPF, HPF, Notch
and arbitrary shape filters. 64 pairs of data and coefficients are
stored. This enables a 64 tap FIR filter or up to 4 16 tap filters of
either FIR or IIR formulation.
2
2
C provides hardware address detect of a 7-bit address without
C features include:
Slave and master, transmitter, and receiver operation
Byte processing for low CPU overhead
Interrupt or polling CPU interface
Support for bus speeds up to 1 Mbps (3.4 Mbps in UDBs)
7 or 10-bit addressing (10-bit addressing requires firmware
support)
SMBus operation (through firmware support – SMBus
supported in hardware in UDBs)
7-bit hardware address compare
Wake from low-power modes on address match
PSoC
2
2
C peripheral provides a synchronous two wire interface
C
2
C specific support is provided for status detection
®
3: CY8C36 Family Datasheet
2
C pin connections are limited to the
2
C operates as a slave, a master,
2
2
C interfaces can be
C interfaces through the
Page 45 of 111
2
C serial
2
C
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