CY8C3665AXI-010 Cypress Semiconductor Corp, CY8C3665AXI-010 Datasheet - Page 61

• Manufacturer Part Number: CY8C3665AXI-010
• Description: PSOC3
• Manufacturer: Cypress Semiconductor Corp
• Series: PSOC™ 3 CY8C36xxr

Specifications of CY8C3665AXI-010

• Package / Case: *
• Voltage - Supply (vcc/vdd): 1.71 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 67MHz
• Number Of I /o: 62
• Eeprom Size: 1K x 8
• Core Processor: 8051
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Program Memory Size: 32KB (32K x 8)
• Data Converters: A/D 2x12b, D/A 4x8b
• Oscillator Type: Internal
• Peripherals: CapSense, DMA, POR, PWM, WDT
• Connectivity: EBI/EMI, I²C, LIN, SPI, UART/USART
• Core Size: 8-Bit
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Technology: CMOS
• Processing Unit: Microcontroller
• Operating Supply Voltage (min): 1.8V
• Operating Supply Voltage (typ): 2.5/3.3/5V
• Operating Supply Voltage (max): 5.5V
• Package Type: TQFP
• Screening Level: Industrial
• Pin Count: 100
• Mounting: Surface Mount
• Rad Hardened: No
• Processor Series: CY8C36
• Core: 8051
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, SPI, UART, USB
• Maximum Clock Frequency: 67 MHz
• Number Of Programmable I/os: 28 to 72
• Number Of Timers: 4
• Operating Supply Voltage: 0.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Controller Family/series: (8051) PSOC 3
• No. Of I/o's: 62
• Eeprom Memory Size: 1KB
• Ram Memory Size: 4KB
• Cpu Speed: 67MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 11-3. AC Specifications
Document Number: 001-53413 Rev. *J
Note
F
F
Svdd
T
T
T
T
28. Based on device characterization (Not production tested).
STARTUP
SLEEP
IO_INIT
CPU
BUSCLK
HIBERNATE
Parameter
CPU frequency
Bus frequency
V
Time from V
≥ IPOR to I/O ports set to their reset
states
Time from V
≥ PRES to CPU executing code at
reset vector
Wakeup from sleep mode –
Application of non–LVD interrupt to
beginning of execution of next CPU
instruction
Wakeup from hibernate mode –
Application of external interrupt to
beginning of execution of next CPU
instruction
DD
ramp rate
Description
DDD
DDD
[28]
/V
/V
DDA
DDA
1.71 V
/V
/V
5.5 V
3.3 V
0.5 V
0 V
CCD
CCD
DC
PRELIMINARY
/V
/V
CCA
CCA
Figure 11-1. F
Valid Operating Region with SMP
1.71 V ≤ V
1.71 V ≤ V
V
V
boot mode (48 MHz typ.)
V
V
IMO boot mode (12 MHz typ.)
CCA
DDA
CCA
DDA
Valid Operating Region
/V
/V
/V
/V
CPU Frequency
1 MHz
DDA
DDD
CCD
DDD
DDD
DDD
Conditions
, no PLL used, fast IMO
, no PLL used, slow
= regulated from
= regulated from
CPU
≤ 5.5 V
≤ 5.5 V
PSoC
vs. V
DD
10 MHz
®
3: CY8C36 Family Datasheet
67 MHz
Min
DC
DC
–
–
–
–
–
–
Typ
–
–
–
–
–
–
–
–
Max
100
67
67
10
33
66
15
1
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Units
MHz
MHz
V/ns
µs
µs
µs
µs
µs
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