CY8CTST200-32LQXIT Cypress Semiconductor Corp, CY8CTST200-32LQXIT Datasheet - Page 140
CY8CTST200-32LQXIT
Manufacturer Part Number
CY8CTST200-32LQXIT
Description
CY8CTST200-32LQXIT
Manufacturer
Cypress Semiconductor Corp
Series
TrueTouch™r
Datasheet
1.CY8CTST200-16LGXI.pdf
(308 pages)
Specifications of CY8CTST200-32LQXIT
Applications
Touchscreen Controller
Core Processor
M8C
Program Memory Type
FLASH (32 kB)
Controller Series
CY8CT
Ram Size
2K x 8
Interface
I²C, SPI, UART/USART, USB
Number Of I /o
28
Voltage - Supply
1.8 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
32-UQFN Exposed Pad, 32-HUQFN, 32-SQFN
Processor Series
CY8CTxx2xx
Core
M8C
Data Bus Width
8 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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System Resets
140
IMO (not to scale)
IMO (not to scale)
IMO (not to scale)
POR (IPOR followed by PPOR): Reset while POR is high (IMO off), then 511(+)
cycles (IMO on), and then the CPU reset is released. XRES is the same, with N=8.
PPOR (with no IPOR): Reset while PPOR is high and to the end of the next 32K
cycle (IMO off); 1 cycle IMO on before the CPU reset is released. Note that at the
3V level, PPOR tends to be brief because the reset clears the POR range register
(VLT_CR) back to the default 2.4V setting.
XRES: Reset while XRES is high (IMO off), then 7(+) cycles (IMO on), and then the
CPU reset is released.
Sleep Timer
Sleep Timer
Sleep Timer
CPU Reset
CPU Reset
CPU Reset
IMO PD
IMO PD
IMO PD
Figure 16-4. Key Signals During POR and XRES
CLK32
PPOR
CLK32
PPOR
Reset
Reset
CLK32
XRES
Reset
IPOR
PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
(Follows POR / XRES)
0
0
0
0
1
1
1
2
2
511
7
N=512
8
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