CY8CTST200-32LQXIT Cypress Semiconductor Corp, CY8CTST200-32LQXIT Datasheet - Page 55
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CY8CTST200-32LQXIT
Manufacturer Part Number
CY8CTST200-32LQXIT
Description
CY8CTST200-32LQXIT
Manufacturer
Cypress Semiconductor Corp
Series
TrueTouch™r
Datasheet
1.CY8CTST200-16LGXI.pdf
(308 pages)
Specifications of CY8CTST200-32LQXIT
Applications
Touchscreen Controller
Core Processor
M8C
Program Memory Type
FLASH (32 kB)
Controller Series
CY8CT
Ram Size
2K x 8
Interface
I²C, SPI, UART/USART, USB
Number Of I /o
28
Voltage - Supply
1.8 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
32-UQFN Exposed Pad, 32-HUQFN, 32-SQFN
Processor Series
CY8CTxx2xx
Core
M8C
Data Bus Width
8 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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- Download datasheet (3Mb)
This chapter discusses the General Purpose I/O (GPIO) and its associated registers, which is the circuit responsible for inter-
facing to the I/O pins of a PSoC device. The GPIO blocks provide the interface between the M8C core and the outside world.
They offer a large number of configurations to support several types of input/output (IO) operations for both digital and analog
systems. For a complete table of the GPIO registers, refer to the
registers in address order, refer to the
6.1
The GPIO in the CY8CTMG20x, CY8CTST200 devices are all uniform, except that Port 0 and Port 1 GPIO have stronger
high drive. In addition to higher drive strength, Port 1 GPIO have an option for regulated output level. These distinctions are
discussed in more detail in the section
PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
6. General Purpose I/O (GPIO)
Drive Modes
DM1
Architectural Description
Write PRTxDR
0
0
1
1
Note Alt. Select/
Data is not available
on all pins.
Alt. Select
DM0
Alt. Data
0
1
0
1
Drive Mode
Resistive Pull Up
Strong Drive
High Impedance
Open Drain
2:1
DM1
DM0
Diagram
Number
Drive
Logic
Register Reference chapter on page
Port 1 Distinctions on page 56
0
1
2
3
REG_EN
Figure 6-1. GPIO Block Diagram
Data = 0
Strong
Strong
An. High Z
Strong
Vdd
5.6k
LDO
Vdd
Data = 1
Note No diode to
Resistive
Strong
High Z
High Z
Vdd for Port 1
Vdd
Port 1
Only
PSoC Core on page
0.
and
Port 0 Distinctions on page
187.
DM(1:0) = 10b
1.
23. For a quick reference of all PSoC
Read PRTxDR
2.
Pin
57.
interrupt logic)
(e.g., I2C)
Data
Alt. Input
Bus
(to GPIO
3.
INBUF
[+] Feedback
55
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