DAC1005D650HW/C1:5 NXP Semiconductors, DAC1005D650HW/C1:5 Datasheet - Page 23

• Manufacturer Part Number: DAC1005D650HW/C1:5
• Description: DAC1005D650HW/HTQFP100/TRAYBDP
• Manufacturer: NXP Semiconductors

Specifications of DAC1005D650HW/C1:5

• Settling Time: 20ns
• Number Of Bits: 10
• Data Interface: SPI™
• Number Of Converters: 2
• Voltage Supply Source: Analog and Digital
• Power Dissipation (max): 1.4W
• Operating Temperature: -45°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP Exposed Pad, 100-eTQFP, 100-HTQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935286776551

NXP Semiconductors
DAC1005D650
Product data sheet
10.5 Timing
The DAC1005D650 can operate at an update rate (f
data rate (f
diagram”.
The typical performances are measured at 50 % duty cycle but any timing within the limits
of the characteristics will not alter the performance.
In
The setting applied to PLL_DIV[1:0] (register 02h[4:3]; see
(address 02h) bit
core to be adjusted.
Fig 8.
Fig 9.
Fig 10. Input timing diagram
Table 31
(CLKP-CLKN)
LVDS clock configuration
Interfacing CML to LVDS
n in Qn = 0 to 9 and for In is 0 to 9.
data
“Frequencies”, the links between internal and external clocking are defined.
In/Qn
CLK
) of up to 160 MHz. The input timing is shown in
All information provided in this document is subject to legal disclaimers.
description”) allows the frequency between the digital part and the DAC
L
Rev. 2 — 3 September 2010
Z
diff = 100 Ω
Dual 10-bit DAC, up to 650 Msps; 2× 4× and 8× interpolating
LVDS
90 %
t
su(i)
Z
diff
= 100 Ω
100 Ω
100 nF
100 nF
N
50 %
V
DDA(1V8)
AGND
t
h(i)
90 %
1.1 kΩ
2.2 kΩ
100 Ω
CLKN
CLKP
55 Ω
55 Ω
100 nF
CLKN
CLKP
s
) of up to 650 Msps and with an input
N + 1
001aah021
t
w(CLK)
LVDS
DAC1005D650
Table 12 “PLLCFG register
001aah020
Figure 10 “Input timing
LVDS
N + 2
© NXP B.V. 2010. All rights reserved.
001aaj815
23 of 42