DSPIC33FJ128GP706A-H/PT Microchip Technology, DSPIC33FJ128GP706A-H/PT Datasheet - Page 158
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DSPIC33FJ128GP706A-H/PT
Manufacturer Part Number
DSPIC33FJ128GP706A-H/PT
Description
16 Bit MCU/DSP 64LD 40MIPS 128KB FLASH 64 TQFP 10x10x1mm TRAY
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Datasheet
1.DSPIC33FJ64GP206A-IMR.pdf
(338 pages)
Specifications of DSPIC33FJ128GP706A-H/PT
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
CAN, I²C, IrDA, LIN, SPI, UART/USART
Peripherals
AC'97, Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 18x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 140°C
Package / Case
64-TQFP
Processor Series
dsPIC33F
Core
dsPIC
Data Bus Width
16 bit
Interface Type
SPI, I2C, UART, JTAG
Number Of Programmable I/os
35
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 140 C
Mounting Style
SMD/SMT
Development Tools By Supplier
MPLAB IDE Software
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 13 Channel
A/d Bit Size
10 bit
A/d Channels Available
13
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC33FJ128GP706A-H/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
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dsPIC33FJXXXGPX06A/X08A/X10A
10.2.2
Idle mode has these features:
• The CPU stops executing instructions.
• The WDT is automatically cleared.
• The system clock source remains active. By
• If the WDT or FSCM is enabled, the LPRC also
The device will wake from Idle mode on any of these
events:
• Any interrupt that is individually enabled.
• Any device Reset.
• A WDT time-out.
On wake-up from Idle, the clock is reapplied to the CPU
and instruction execution will begin (2-4 clock cycles
later), starting with the instruction following the PWRSAV
instruction, or the first instruction in the ISR.
10.2.3
Any interrupt that coincides with the execution of a
PWRSAV instruction is held off until entry into Sleep or
Idle mode has completed. The device then wakes up
from Sleep or Idle mode.
10.3
Generally, changing clock speed and invoking one of the
power-saving modes are the preferred strategies for
reducing
circumstances, however, where this is not practical. For
example, it may be necessary for an application to
maintain uninterrupted synchronous communication,
even while it is doing nothing else. Reducing system
clock speed may introduce communication errors, while
using a power-saving mode may stop communications
Doze mode is a simple and effective alternative method
to reduce power consumption while the device is still
executing code. In this mode, the system clock
continues to operate from the same source and at the
same speed. Peripheral modules continue to be
clocked at the same speed, while the CPU clock speed
is reduced. Synchronization between the two clock
domains is maintained, allowing the peripherals to
access the SFRs while the CPU executes code at a
slower rate.
DS70593B-page 158
default, all peripheral modules continue to operate
normally from the system clock source, but can
also be selectively disabled (see Section 10.4
“Peripheral Module Disable”).
remains active.
Doze Mode
power
IDLE MODE
INTERRUPTS COINCIDENT WITH
POWER SAVE INSTRUCTIONS
consumption.
There
may
Preliminary
be
Doze mode is enabled by setting the DOZEN bit (CLK-
DIV<11>). The ratio between peripheral and core clock
speed is determined by the DOZE<2:0> bits (CLK-
DIV<14:12>). There are eight possible configurations,
from 1:1 to 1:128, with 1:1 being the default setting.
It is also possible to use Doze mode to selectively
reduce
applications. This allows clock-sensitive functions,
such as synchronous communications, to continue
without interruption while the CPU idles, waiting for
something to invoke an interrupt routine. Enabling the
automatic return to full-speed CPU operation on
interrupts is enabled by setting the ROI bit (CLK-
DIV<15>). By default, interrupt events have no effect
on Doze mode operation.
For example, suppose the device is operating at
20 MIPS and the CAN module has been configured for
500 kbps based on this device operating speed. If the
device is now placed in Doze mode with a clock
frequency ratio of 1:4, the CAN module continues to
communicate at the required bit rate of 500 kbps, but
the CPU now starts executing instructions at a
frequency of 5 MIPS.
10.4
The Peripheral Module Disable (PMD) registers
provide a method to disable a peripheral module by
stopping all clock sources supplied to that module.
When a peripheral is disabled via the appropriate PMD
control bit, the peripheral is in a minimum power
consumption state. The control and status registers
associated with the peripheral are also disabled, so
writes to those registers will have no effect and read
values will be invalid.
A peripheral module is only enabled if both the
associated bit in the PMD register is cleared and the
peripheral is supported by the specific dsPIC
variant. If the peripheral is present in the device, it is
enabled in the PMD register by default.
Note:
Peripheral Module Disable
power
If a PMD bit is set, the corresponding
module is disabled after a delay of 1
instruction cycle. Similarly, if a PMD bit is
cleared, the corresponding module is
enabled after a delay of 1 instruction cycle
(assuming the module control registers
are already configured to enable module
operation).
consumption
2009 Microchip Technology Inc.
in
event-driven
®
DSC
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