DSPIC33FJ128GP706A-H/PT Microchip Technology, DSPIC33FJ128GP706A-H/PT Datasheet - Page 187
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DSPIC33FJ128GP706A-H/PT
Manufacturer Part Number
DSPIC33FJ128GP706A-H/PT
Description
16 Bit MCU/DSP 64LD 40MIPS 128KB FLASH 64 TQFP 10x10x1mm TRAY
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Datasheet
1.DSPIC33FJ64GP206A-IMR.pdf
(338 pages)
Specifications of DSPIC33FJ128GP706A-H/PT
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
CAN, I²C, IrDA, LIN, SPI, UART/USART
Peripherals
AC'97, Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 18x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 140°C
Package / Case
64-TQFP
Processor Series
dsPIC33F
Core
dsPIC
Data Bus Width
16 bit
Interface Type
SPI, I2C, UART, JTAG
Number Of Programmable I/os
35
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 140 C
Mounting Style
SMD/SMT
Development Tools By Supplier
MPLAB IDE Software
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 13 Channel
A/d Bit Size
10 bit
A/d Channels Available
13
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC33FJ128GP706A-H/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
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17.0
The Inter-Integrated Circuit (I
complete hardware support for both Slave and
Multi-Master modes of the I
standard, with a 16-bit interface.
The
have up to two I
and I2C2. Each I
SCLx pin is clock and the SDAx pin is data.
Each I
features:
• I
• I
• I
• I
• Serial clock synchronization for I
• I
2009 Microchip Technology Inc.
operation.
master and slaves.
used as a handshake mechanism to suspend and
resume serial transfer (SCLREL control).
collision and will arbitrate accordingly.
2
2
2
2
2
Note 1: This data sheet summarizes the features
C interface supporting both master and slave
C Slave mode supports 7 and 10-bit address.
C Master mode supports 7 and 10-bit address.
C Port allows bidirectional transfers between
C supports multi-master operation; detects bus
2
dsPIC33FJXXXGPX06A/X08A/X10A
C module ‘x’ (x = 1 or 2) offers the following key
2: Some registers and associated bits
INTER-INTEGRATED
CIRCUIT™ (I
of
X10A family of devices. However, it is not
intended to be a comprehensive refer-
ence source. To complement the informa-
tion in this data sheet, refer to Section
19. “Inter-Integrated Circuit™ (I
(DS70195) in the “dsPIC33F/PIC24H
Family Reference Manual”, which is avail-
able from the Microchip web site
(www.microchip.com).
described in this section may not be avail-
able on all devices. Refer to Section 4.0
“Memory Organization” in this data
sheet for device-specific register and bit
information.
2
the dsPIC33FJXXXGPX06A/X08A/
C interface modules, denoted as I2C1
2
C module has a 2-pin interface: the
dsPIC33FJXXXGPX06A/X08A/X10A
2
C™)
2
C serial communication
2
C) module provides
2
C port can be
2
devices
C™)”
Preliminary
17.1
The hardware fully implements all the master and slave
functions of the I
specifications, as well as 7 and 10-bit addressing.
The I
master on an I
The following types of I
• I
• I
• I
For details about the communication sequence in each
of these modes, please refer to the “dsPIC33F/PIC24H
Family Reference Manual”.
17.2
I2CxCON and I2CxSTAT are control and status
registers, respectively. The I2CxCON register is
readable and writable. The lower six bits of I2CxSTAT
are read-only. The remaining bits of the I2CSTAT are
read/write.
I2CxRSR is the shift register used for shifting data,
whereas I2CxRCV is the buffer register to which data
bytes are written, or from which data bytes are read.
I2CxRCV is the receive buffer. I2CxTRN is the transmit
register to which bytes are written during a transmit
operation.
The I2CxADD register holds the slave address. A
status bit, ADD10, indicates 10-bit Address mode. The
I2CxBRG acts as the Baud Rate Generator (BRG)
reload value.
In receive operations, I2CxRSR and I2CxRCV together
form a double-buffered receiver. When I2CxRSR
receives a complete byte, it is transferred to I2CxRCV
and an interrupt pulse is generated.
2
2
2
C slave operation with 7-bit address
C slave operation with 10-bit address
C master operation with 7 or 10-bit address
2
C module can operate either as a slave or a
Operating Modes
I
2
C Registers
2
C bus.
2
C Standard and Fast mode
2
C operation are supported:
DS70593B-page 187
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