DSPIC33FJ64MC202-E/MM Microchip Technology, DSPIC33FJ64MC202-E/MM Datasheet - Page 63
![16 Bit MCU/DSP 40MIPS 64 KB FLASH 28 QFN-S 6x6mm TUBE](/photos/6/81/68120/150-28-qfn_sml.jpg)
DSPIC33FJ64MC202-E/MM
Manufacturer Part Number
DSPIC33FJ64MC202-E/MM
Description
16 Bit MCU/DSP 40MIPS 64 KB FLASH 28 QFN-S 6x6mm TUBE
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Specifications of DSPIC33FJ64MC202-E/MM
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
21
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 6x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
28-QFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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TABLE 4-27:
TABLE 4-28:
PMCON
PMMODE
PMADDR
PMDOUT1
PMDOUT2
PMDIN1
PMPDIN2
PMAEN
PMSTAT
Legend:
PMCON
PMMODE
PMADDR
PMDOUT1
PMDOUT2
PMDIN1
PMPDIN2
PMAEN
PMSTAT
Legend:
File Name
File Name
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Addr
0600
0606
060A
060C
060E
Addr
0604
060A
060C
060E
0602
0604
0608
0600
0602
0606
0608
PARALLEL MASTER/SLAVE PORT REGISTER MAP FOR dsPIC33FJ128MC202/802, dsPIC33FJ64MC202/802 AND
dsPIC33FJ32MC302
PARALLEL MASTER/SLAVE PORT REGISTER MAP FOR dsPIC33FJ128MC204/804, dsPIC33FJ64MC204/804 AND
dsPIC33FJ32MC304
ADDR15
ADDR15
PMPEN
PMPEN
Bit 15
BUSY
Bit 15
BUSY
IBF
IBF
—
—
PTEN14
PTEN14
Bit 14
Bit 14
IBOV
IBOV
CS1
CS1
—
—
IRQM<1:0>
IRQM<1:0>
PSIDL
PSIDL
Bit 13
Bit 13
—
—
—
—
Bit 12
Bit 12
ADRMUX<1:0>
ADRMUX<1:0>
—
—
—
—
INCM<1:0>
INCM<1:0>
Bit 11
Bit 11
IB3F
IB3F
—
—
MODE16
MODE16
PTBEEN PTWREN PTRDEN
PTBEEN PTWREN PTRDEN
Bit 10
Bit 10
IB2F
IB2F
—
Parallel Port Data Out Register 1 (Buffers 0 and 1)
Parallel Port Data Out Register 2 (Buffers 2 and 3)
Parallel Port Data Out Register 1 (Buffers 0 and 1)
Parallel Port Data Out Register 2 (Buffers 2 and 3)
Parallel Port Data In Register 1 (Buffers 0 and 1)
Parallel Port Data In Register 2 (Buffers 2 and 3)
Parallel Port Data In Register 1 (Buffers 0 and 1)
Parallel Port Data In Register 2 (Buffers 2 and 3)
Bit 9
Bit 9
IB1F
IB1F
—
MODE<1:0>
MODE<1:0>
Bit 8
IB0F
Bit 8
IB0F
—
CSF1
CSF1
Bit 7
OBE
Bit 7
OBE
ADDR<13:0>
ADDR<13:0>
—
WAITB<1:0>
WAITB<1:0>
OBUF
OBUF
CSF0
CSF0
Bit 6
Bit 6
—
PTEN<10:0>
Bit 5
Bit 5
ALP
ALP
—
—
—
Bit 4
Bit 4
—
—
—
—
—
WAITM<3:0>
WAITM<3:0>
OB3E
OB3E
CS1P
CS1P
Bit 3
Bit 3
—
OB2E
OB2E
Bit 2
Bit 2
BEP
BEP
—
WRSP
WRSP
OB1E
OB1E
Bit 1
Bit 1
WAITE<1:0>
WAITE<1:0>
PTEN<1:0>
RDSP
OB0E
RDSP
OB0E
Bit 0
Bit 0
Resets
Resets
0000
0000
0000
0000
0000
0000
0000
0000
008F
0000
0000
0000
0000
0000
0000
0000
0000
008F
All
All
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