EP20K100QC208-1 Altera, EP20K100QC208-1 Datasheet - Page 114

• Manufacturer Part Number: EP20K100QC208-1
• Description: APEX 20K
• Manufacturer: Altera

Specifications of EP20K100QC208-1

• Family Name: APEX 20K
• Number Of Usable Gates: 100000
• Number Of Logic Blocks/elements: 4160
• # Registers: 26
• # I/os (max): 159
• Frequency (max): 250MHz
• Process Technology: SRAM
• Operating Supply Voltage (typ): 2.5V
• Logic Cells: 4160
• Ram Bits: 53248
• Device System Gates: 263000
• Operating Supply Voltage (min): 2.375V
• Operating Supply Voltage (max): 2.625V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: PQFP
• Lead Free Status / Rohs Status: Not Compliant

APEX 20K Programmable Logic Device Family Data Sheet
Device Pin-Outs
114
Configuration device
Passive serial (PS)
Passive parallel asynchronous (PPA)
Passive parallel synchronous (PPS)
JTAG
Table 111. Data Sources for Configuration
Configuration Scheme
f
SRAM configuration elements allow APEX 20K devices to be
reconfigured in-circuit by loading new configuration data into the
device. Real-time reconfiguration is performed by forcing the device
into command mode with a device pin, loading different
configuration data, reinitializing the device, and resuming user-
mode operation. In-field upgrades can be performed by distributing
new configuration files.
Configuration Schemes
The configuration data for an APEX 20K device can be loaded with
one of five configuration schemes (see
of the target application. An EPC2 or EPC16 configuration device,
intelligent controller, or the JTAG port can be used to control the
configuration of an APEX 20K device. When a configuration device
is used, the system can configure automatically at system power-up.
Multiple APEX 20K devices can be configured in any of five
configuration schemes by connecting the configuration enable (nCE)
and configuration enable output (nCEO) pins on each device.
For more information on configuration, see Application Note 116
(Configuring APEX 20K, FLEX 10K, & FLEX 6000 Devices.)
See the Altera web site (http://www.altera.com) or the Altera Digital
Library for pin-out information
EPC1, EPC2, EPC16 configuration devices
MasterBlaster or ByteBlasterMV download cable or serial data source
Parallel data source
Parallel data source
MasterBlaster or ByteBlasterMV download cable or a microprocessor
with a Jam or JBC File
Data Source
Table
111), chosen on the basis
Altera Corporation