EP20K100QC208-1 Altera, EP20K100QC208-1 Datasheet - Page 7

APEX 20K

EP20K100QC208-1

Manufacturer Part Number
EP20K100QC208-1
Description
APEX 20K
Manufacturer
Altera
Datasheet

Specifications of EP20K100QC208-1

Family Name
APEX 20K
Number Of Usable Gates
100000
Number Of Logic Blocks/elements
4160
# Registers
26
# I/os (max)
159
Frequency (max)
250MHz
Process Technology
SRAM
Operating Supply Voltage (typ)
2.5V
Logic Cells
4160
Ram Bits
53248
Device System Gates
263000
Operating Supply Voltage (min)
2.375V
Operating Supply Voltage (max)
2.625V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
208
Package Type
PQFP
Lead Free Status / Rohs Status
Not Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP20K100QC208-1
Manufacturer:
ALTERA
0
Altera Corporation
MultiCore system integration
SignalTap logic analysis
32/64-Bit, 33-MHz PCI
32/64-Bit, 66-MHz PCI
MultiVolt I/O
ClockLock support
Dedicated clock and input pins Six
I/O standard support
Memory support
Table 8. Comparison of APEX 20K & APEX 20KE Features
Feature
Full support
Full support
Full compliance in -1, -2 speed
grades
2.5-V or 3.3-V V
V
Certain devices are 5.0-V tolerant
Clock delay reduction
2× and 4× clock multiplication
2.5-V, 3.3-V, 5.0-V I/O
3.3-V PCI
Low-voltage complementary
metal-oxide semiconductor
(LVCMOS)
Low-voltage transistor-to-transistor
logic (LVTTL)
Dual-port RAM
FIFO
RAM
ROM
CCIO
selected for device
APEX 20K Devices
CCIO
APEX 20K Programmable Logic Device Family Data Sheet
-
Full compliance in -1, -2 speed grades
Full compliance in -1 speed grade
1.8-V, 2.5-V, or 3.3-V V
V
5.0-V tolerant with use of external resistor
Clock delay reduction
m /(n × v) or m /(n × k) clock multiplication
Drive ClockLock output off-chip
External clock feedback
ClockShift
LVDS support
Up to four PLLs
ClockShift, clock phase adjustment
Eight
1.8-V, 2.5-V, 3.3-V, 5.0-V I/O
2.5-V I/O
3.3-V PCI and PCI-X
3.3-V Advanced Graphics Port (AGP)
Center tap terminated (CTT)
GTL+
LVCMOS
LVTTL
True-LVDS and LVPECL data pins
(in EP20K300E and larger devices)
LVDS and LVPECL signaling (in all BGA
and FineLine BGA devices)
LVDS and LVPECL data pins up to
156 Mbps (in -1 speed grade devices)
HSTL Class I
PCI-X
SSTL-2 Class I and II
SSTL-3 Class I and II
CAM
Dual-port RAM
FIFO
RAM
ROM
Full support
Full support
CCIO
selected block-by-block
APEX 20KE Devices
CCIO
7

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