EP20K100QC208-1 Altera, EP20K100QC208-1 Datasheet - Page 57

• Manufacturer Part Number: EP20K100QC208-1
• Description: APEX 20K
• Manufacturer: Altera

Specifications of EP20K100QC208-1

• Family Name: APEX 20K
• Number Of Usable Gates: 100000
• Number Of Logic Blocks/elements: 4160
• # Registers: 26
• # I/os (max): 159
• Frequency (max): 250MHz
• Process Technology: SRAM
• Operating Supply Voltage (typ): 2.5V
• Logic Cells: 4160
• Ram Bits: 53248
• Device System Gates: 263000
• Operating Supply Voltage (min): 2.375V
• Operating Supply Voltage (max): 2.625V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: PQFP
• Lead Free Status / Rohs Status: Not Compliant

Altera Corporation
Notes to
(1)
(2)
Figure 31. APEX 20K JTAG Waveforms
EP20K30E
EP20K60E
EP20K100
EP20K100E
EP20K160E
EP20K200
EP20K200E
EP20K300E
EP20K400
EP20K400E
EP20K600E
EP20K1000E
Table 21. 32-Bit APEX 20K Device IDCODE
Captured
Driven
Signal
Signal
The most significant bit (MSB) is on the left.
The IDCODE’s least significant bit (LSB) is always 1.
to Be
to Be
TMS
TDO
TCK
Device
TDI
Table
21:
t
JCH
t
t
JPZX
JSZX
Version
(4 Bits)
t
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
JCP
t
JSSU
t
JCL
Figure 31
t
JSH
1000 0000 0011 0000
1000 0000 0110 0000
0000 0100 0001 0110
1000 0001 0000 0000
1000 0001 0110 0000
0000 1000 0011 0010
1000 0010 0000 0000
1000 0011 0000 0000
0001 0110 0110 0100
1000 0100 0000 0000
1000 0110 0000 0000
1001 0000 0000 0000
t
Part Number (16 Bits)
t
JPCO
shows the timing requirements for the JTAG signals.
JSCO
t
JPSU
APEX 20K Programmable Logic Device Family Data Sheet
IDCODE (32 Bits)
t
t
JSXZ
JPH
t
JPXZ
(1)
000 0110 1110
000 0110 1110
000 0110 1110
000 0110 1110
000 0110 1110
000 0110 1110
000 0110 1110
000 0110 1110
000 0110 1110
000 0110 1110
000 0110 1110
000 0110 1110
Identity (11 Bits)
Manufacturer
1 (1 Bit)
(2)
1
1
1
1
1
1
1
1
1
1
1
1
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