EVAL-AD1937AZ Analog Devices Inc, EVAL-AD1937AZ Datasheet - Page 28

• Manufacturer Part Number: EVAL-AD1937AZ
• Description: EB Single Chip Codec 4 ADCs W/Diff Outp
• Manufacturer: Analog Devices Inc

Specifications of EVAL-AD1937AZ

• Main Purpose: Audio, CODEC
• Utilized Ic / Part: AD1937
• Primary Attributes: 24-Bit, 192 kHz, 4 ADCs: 107dB Dynamic Range, 8 DACs: 112dB Dynamic Range
• Secondary Attributes: Time Division Multiplexed (TDM), I2C, and SPI Interface, Popguard® Technology
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Embedded: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD1937
Table 23. PLL and Clock Control 1 Register (Address 1, 0x01)
Bit
0
1
2
3
7:4
DAC CONTROL REGISTERS
Table 24. DAC Control 0 Register (Address 2, 0x02)
Bit
0
2:1
5:3
7:6
Value
0
1
0
1
0
1
0
1
0000
Value
0
1
00
01
10
11
000
001
010
011
100
101
110
111
00
01
10
11
Function
PLL clock
MCLK
PLL clock
MCLK
Enabled
Disabled
Not locked
Locked
Reserved
Function
Normal
Power-down
32 kHz/44.1 kHz/48 kHz
64 kHz/88.2 kHz/96 kHz
128 kHz/176.4 kHz/192 kHz
Reserved
1 cycle (I
0 (left-justified mode)
8 cycles (right-justified 24-bit mode)
12 cycles (right-justified 20-bit mode)
16 cycles (right-justified 16-bit mode)
Reserved
Reserved
Reserved
Stereo (normal)
TDM single-line, standalone, and daisy-chain modes
TDM/AUX mode (ADC-, DAC-, TDM-coupled)
TDM dual-line daisy-chain mode
2
S mode)
Rev. B | Page 28 of 36
Description
DAC clock source select
ADC clock source select
On-chip voltage reference
PLL lock indicator (read-only)
Description
Power-down
Sample rate
DSDATA delay (BCLK periods)
Serial format