EVAL-AD1937AZ Analog Devices Inc, EVAL-AD1937AZ Datasheet - Page 8

• Manufacturer Part Number: EVAL-AD1937AZ
• Description: EB Single Chip Codec 4 ADCs W/Diff Outp
• Manufacturer: Analog Devices Inc

Specifications of EVAL-AD1937AZ

• Main Purpose: Audio, CODEC
• Utilized Ic / Part: AD1937
• Primary Attributes: 24-Bit, 192 kHz, 4 ADCs: 107dB Dynamic Range, 8 DACs: 112dB Dynamic Range
• Secondary Attributes: Time Division Multiplexed (TDM), I2C, and SPI Interface, Popguard® Technology
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Embedded: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD1937
TIMING SPECIFICATIONS
−40°C < T
Table 8.
Parameter
INPUT MASTER CLOCK (MCLK) AND RESET
PLL
I
DAC SERIAL PORT
ADC SERIAL PORT
AUXILIARY INTERFACE
2
C
t
t
f
f
t
t
Lock Time
256 f
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
MH
MH
MCLK
MCLK
PDR
PDRR
SCL
SCLL
SCLH
SCS
SCH
SSH
DS
SR
SF
BFT
DBH
DBL
DLS
DLH
DDS
DDH
ABH
ABL
ALS
ALH
ABDD
AXDS
AXDH
DXDD
XBH
XBL
DLS
DLH
MCLKO/MCLKXO Pin
S
VCO Clock, Output Duty Cycle,
C
< +125°C, DVDD = 3.3 V ± 10%.
Condition
MCLK duty cycle
MCLK frequency
Low
Recovery
MCLK or LRCLK
SCL clock frequency
SCL low
SCL high
Setup time (start condition)
Hold time (start condition)
Setup time (stop condition)
Data setup time
SDA and SCL rise time
SDA and SCL fall time
Bus-free time
DBCLK high
DBCLK low
DLRCLK setup
DLRCLK skew
DLRCLK hold
DSDATA setup
DSDATA hold
ABCLK high
ABCLK low
ALRCLK setup
ALRCLK skew
ALRCLK hold
ASDATA delay
AAUXDATA setup
AAUXDATA hold
DAUXDATA delay
AUXBCLK high
AUXBCLK low
AUXLRCLK setup
AUXLRCLK hold
Rev. B | Page 8 of 36
Comments
DAC/ADC clock source = PLL clock
@ 256 f
DAC/ADC clock source = direct MCLK
@ 512 f
PLL mode, 256 f
Direct 512 f
Reset to active output
See Figure 13 and Figure 14
Relevent for repeated start condition
First clock generated after this period
Between stop and start
See Figure 2
Slave mode
Slave mode
To DBCLK rising, slave mode
From DBCLK falling, master mode
From DBCLK rising, slave mode
To DBCLK rising
From DBCLK rising
See Figure 3
Slave mode
Slave mode
To ABCLK rising, slave mode
From ABCLK falling, master mode
From ABCLK rising, slave mode
From ABCLK falling, any mode
To AUXBCLK rising
From AUXBCLK rising
From AUXBCLK falling
To AUXBCLK rising
From AUXBCLK rising
S
S
, 384 f
(bypass on-chip PLL)
S
mode
S
, 512 f
S
reference
S
, and 768 f
S
Min
40
40
6.9
15
4096
40
1.3
0.6
0.6
0.6
0.6
100
1.3
10
10
10
−8
5
10
5
10
10
10
−8
5
10
5
10
10
10
5
Max
60
60
13.8
27.6
10
60
400
300
300
+8
+8
18
18
Unit
%
%
MHz
MHz
ns
t
ms
%
kHz
μs
μs
μs
μs
μs
ns
ns
ns
μs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MCLK