ISL65426EVAL1Z Intersil, ISL65426EVAL1Z Datasheet - Page 20

• Manufacturer Part Number: ISL65426EVAL1Z
• Description: ISL65426 EVAL BOARD 1 - RoHS COMPLIANT - QFN
• Manufacturer: Intersil

Layout Considerations
Careful printed circuit board (PCB) layout is critical in high-
frequency switching converter design. Current transitions
from one device to another at this frequency induce voltage
spikes across the interconnecting impedances and parasitic
elements. These spikes degrade efficiency, lead to device
overvoltage stress, radiate noise into sensitive nodes, and
increase thermal stress on critical components. Careful
component placement and PCB layout minimizes the
voltage spikes in the converter.
The following multi-layer printed circuitry board layout
strategies minimize the impact of board parasitics on
converter performance and optimize the heat-dissipating
capabilities of the printed circuit board. This section
highlights some important practices which should not be
overlooked during the layout process. Figure 6 provides a
top level view of the critical components, layer utilization,
and signal routing for reference.
Component Placement
Determine the total implementation area and orient the
critical switching components first. These include the
controller, input and output capacitors, and the output
inductors. Symmetry is very important in determining how
V
C
IN
BP
GND
VCC
ISL65426
20
FIGURE 38. PRINTED CIRCUIT BOARD POWER PLANES AND ISLANDS
PGND
PVIN
LX
FB
PHASE
C
IN
V
ISL65426
IN
L
OUT
available space is filled and depends on the power block
configuration selected. The controller must be placed
equidistant from each output stage with the LX, or phase,
connection distance minimized.
An output stage consists of the area reserved for the output
inductor, and input capacitors, and output capacitors for a
single channel. Place the inductor such that one pad is a
minimal distance from the associated phase connection.
Orient the inductor such that the load device is a short
distance from the other pad. Placement of the input
capacitors a minimal distance from the PVIN pins prevents
long distances from adding too much trace inductance and a
reduction in capacitor performance. Locate the output
capacitors between the inductor and the load device, while
keeping them in close proximity. Care should be taken not to
add inductance through long trace lengths that could cancel
the usefulness of the low inductance components. Keeping
the components in tight proximity will help reduce parasitic
impedances once the components are routed together.
Bypass capacitors, C
placed close to their respective pins. Stray trace parasitics
will reduce their effectiveness, so keep the distance between
the VCC bias supply pad and capacitor pad to a minimum.
VIA CONNECTION TO GROUND PLANE
THICK TRACE ON CIRCUIT PLANE LAYER
ISLAND ON POWER PLANE LAYER
ISLAND ON CIRCUIT PLANE LAYER
C
OUT
V
OUT
C
KEY
BP
HFOUT
, supply critical filtering and must be
LOAD
November 14, 2006
FN6340.1