KSZ8842-PMQL Micrel Inc, KSZ8842-PMQL Datasheet - Page 40
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KSZ8842-PMQL
Manufacturer Part Number
KSZ8842-PMQL
Description
2-Port Ethernet Switch/Repeater + 32-bit/33MHz PCI Bus Interface( )
Manufacturer
Micrel Inc
Specifications of KSZ8842-PMQL
Controller Type
Ethernet Switch Controller
Interface
PCI
Voltage - Supply
3.1 V ~ 3.5 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
128-MQFP, 128-PQFP
Number Of Primary Switch Ports
2
Internal Memory Buffer Size
32
Operating Supply Voltage (typ)
3.3V
Fiber Support
Yes
Integrated Led Drivers
Yes
Phy/transceiver Interface
MII
Power Supply Type
Analog/Digital
Package Type
PQFP
Data Rate (typ)
10/100Mbps
Vlan Support
Yes
Operating Temperature (max)
70C
Operating Temperature (min)
0C
Pin Count
128
Mounting
Surface Mount
Jtag Support
No
Operating Supply Voltage (max)
3.5V
Operating Supply Voltage (min)
3.1V
Operating Temperature Classification
Commercial
Data Rate
100Mbps
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
576-1636 - BOARD EVALUATION KSZ8842-PMQL
Current - Supply
-
Lead Free Status / RoHS Status
Compliant, Lead free / RoHS Compliant
Other names
576-1513-5
KSZ8842-PMQL
KSZ8842-PMQL
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
KSZ8842-PMQLI
Manufacturer:
TI
Quantity:
3 100
Micrel, Inc.
The following table describes the CFCS register bit fields.
October 2007
26 – 25
23 – 22
20 – 9
5 – 3
Bit
24
21
31
30
29
28
27
8
7
6
Command
Command
Reserved
Reserved
Reserved
Reserved
Status
Status
Status
Status
Status
Status
Status
Status
Type
Default
0x000
000
01
00
0
0
0
0
0
0
0
0
0
0
Data Parity Report
This bit is set when the following conditions are met:
The KSZ8842-PMQL/PMBL asserts parity error PERR_N or it
senses the assertion of PERR_N by another device.
The KSZ8842-PMQL/PMBL operates as a bus master for the
operation that caused the error.
Parity error response (CFCS[6]) is set.
Reserved
66MHz Capable
0 = Not 66MHz capable
Reserved
System Error Enable
When set, the KSZ8842-PMQL/PMBL asserts system error
(SERR_N) when it detects a parity error on the address phase.
Reserved
Parity Error Response
When set, the KSZ8842-PMQL/PMBL asserts fatal bus error after it
detects a parity error.
When reset, any detected parity error is ignored and the KSZ8842-
PMQL/PMBL continues normal operation. Parity checking is
disabled after hardware reset.
Reserved
Description
Detected Parity Error
When set, indicates that the KSZ8842-PMQL/PMBL detected a
parity error, even if parity error handling is disabled in parity error
response (CFCS[6]).
Signal System Error
When set, indicates that the KSZ8842-PMQL/PMBL asserted the
system error SERR_N pin/ball.
Received Master Abort
When set, indicates that the KSZ8842-PMQL/PMBL terminated a
master transaction with master abort.
Received Target Abort
When set, indicates that the KSZ8842-PMQL/PMBL master
transaction was terminated due to a target abort.
Target Abort
This bit is set by KSZ8842-PMQL/PMBL whenever it terminates
with a Target Abort. The CSR registers are all 32-bit Little Endian
format.
For PCI register Read cycles, the KSZ8842-PMQL/PMBL allows
any different combination of CBEN. For PCI register bus cycles,
only byte, word (16-bit), or Dword (32-bit) accesses are allowed.
Any other combination is illegal and is target aborted.
Device Select Timing
Indicates the timing of the assertion of device select(DEVSEL_N).
These bits are fixed at 01, which indicates a middle assertion of
DEVSEL_N.
40
KSZ8842-PMQL/PMBL
M9999-100207-1.5