KSZ8842-PMQL Micrel Inc, KSZ8842-PMQL Datasheet - Page 43
![2-Port Ethernet Switch/Repeater + 32-bit/33MHz PCI Bus Interface( )](/photos/6/81/68152/576-128-pqfp_sml.jpg)
KSZ8842-PMQL
Manufacturer Part Number
KSZ8842-PMQL
Description
2-Port Ethernet Switch/Repeater + 32-bit/33MHz PCI Bus Interface( )
Manufacturer
Micrel Inc
Specifications of KSZ8842-PMQL
Controller Type
Ethernet Switch Controller
Interface
PCI
Voltage - Supply
3.1 V ~ 3.5 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
128-MQFP, 128-PQFP
Number Of Primary Switch Ports
2
Internal Memory Buffer Size
32
Operating Supply Voltage (typ)
3.3V
Fiber Support
Yes
Integrated Led Drivers
Yes
Phy/transceiver Interface
MII
Power Supply Type
Analog/Digital
Package Type
PQFP
Data Rate (typ)
10/100Mbps
Vlan Support
Yes
Operating Temperature (max)
70C
Operating Temperature (min)
0C
Pin Count
128
Mounting
Surface Mount
Jtag Support
No
Operating Supply Voltage (max)
3.5V
Operating Supply Voltage (min)
3.1V
Operating Temperature Classification
Commercial
Data Rate
100Mbps
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
576-1636 - BOARD EVALUATION KSZ8842-PMQL
Current - Supply
-
Lead Free Status / RoHS Status
Compliant, Lead free / RoHS Compliant
Other names
576-1513-5
KSZ8842-PMQL
KSZ8842-PMQL
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
KSZ8842-PMQLI
Manufacturer:
TI
Quantity:
3 100
Micrel, Inc.
The following table shows the access rules of the register.
PCI Control & Status Registers
The PCI CSR registers are all 32 bit in Little Endian format. For PCI register Read cycle, the KSZ8842-PMQL/PMBL
allows any different combination of CBEN. For PCI register bus cycles, only byte, word (16-bit), or Dword (32-bit)
accesses are allowed. Any other combinations are illegal, and will be target aborted.
MAC DMA Transmit Control Register (MDTXC Offset 0x0000)
The MAC DMA transmit control register establishes the transmit operating modes and commands for the port. This
register should be one of the last CSRs to be written as part of the transmit initialization.
The following table shows the register bit fields.
October 2007
Category
Value after hardware reset
31 – 30
29 – 24
23 – 19
15 – 10
7 – 0
Bit
Bit
18
17
16
Default
0x00
0x00
0x00
0
0
0
-
Default
0x00
R/W
RW
RW
RW
RW
RO
RO
RO
Description
Reserved
MTBS DMA Transmit Burst Size
This field indicates the maximum number of words to be transferred in one
DMA transaction. If reset, the MAC DMA burst size is limited only by the
amound of data stored in the transmit buffer before issuing a bus request. The
MTBS can be programmed with the following permissible values: 0,1, 2, 4, 8,
16, or 32.
After reset, the MTBS default is 0, i.e., unlimited.
Reserved
MTUCG MAC Transmit UDP Checksum Generate
When set, the KSZ8842-PMQL/PMBL will generate correct UDP checksum for
outgoing UDP/IP frames at port.
When this bit is set, ADD CRC should also turn on.
MTTCG MAC Transmit TCP Checksum Generate
When set, the KSZ8842-PMQL/PMBL will generate correct TCP checksum for
outgoing TCP/IP frames at port.
When this bit is set, ADD CRC should also turn on.
MTICG MAC Transmit IP Checksum Generate
When set, the KSZ8842-PMQL/PMBL will generate correct IP checksum for
outgoing IP frames at port.
When this bit is set, ADD CRC should also turn on.
Reserved
Description
Interrupt Line
Provides interrupt line routing information. The basic input/output system
(BIOS) writes the routing information into to this field when it initialized and
configures the system.
The value in this field indicates which input of the system interrupt controller is
connected to the KSZ8842-PMQL/PMBL’s interrupt pin/ball. The driver uses
this information to determine priority and vector information. Values in this field
are system architecture specific.
Description
0x281401XX
43
KSZ8842-PMQL/PMBL
M9999-100207-1.5