KSZ8997 Micrel Inc, KSZ8997 Datasheet

8 Port 10/100 Switch With PHY And Frame Buffers (Lead Free)

KSZ8997

Manufacturer Part Number
KSZ8997
Description
8 Port 10/100 Switch With PHY And Frame Buffers (Lead Free)
Manufacturer
Micrel Inc
Datasheets

Specifications of KSZ8997

Applications
*
Mounting Type
Surface Mount
Package / Case
128-MQFP, 128-PQFP
Fiber Support
No
Integrated Led Drivers
Yes
Phy/transceiver Interface
MII
Power Supply Type
Analog/Digital
Package Type
PQFP
Data Rate (typ)
10/100Mbps
Vlan Support
Yes
Operating Temperature (max)
70C
Operating Temperature (min)
0C
Pin Count
128
Mounting
Surface Mount
Jtag Support
No
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
576-1043

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
KSZ8997
Manufacturer:
Micrel Inc
Quantity:
10 000
Part Number:
KSZ8997
Manufacturer:
MICREL
Quantity:
1 000
Part Number:
KSZ8997
Manufacturer:
MICREL/麦瑞
Quantity:
20 000
General Description
The KS8997 contains eight 10/100 physical layer transceiv-
ers, eight MAC (Media Access Control) units with an inte-
grated layer 2 switch. The device runs as an eight port
integrated switch
The KS8997 is designed to reside in an unmanaged design
not requiring processor intervention. This is achieved through
I/O strapping or EEPROM programming at system reset time.
On the media side, the KS8997 supports 10BaseT and
100BaseTX through auto-negotiation as specified by the
IEEE 802.3 committee.
Physical signal transmission and reception are enhanced
through use of analog circuitry that makes the design more
efficient and allows for lower power consumption and smaller
chip die size.
Data sheets and support documentation can be found on
Micrel’s web site at www.micrel.com.
Functional Diagram
August 2003
KS8997
Micrel, Inc. • 1849 Fortune Drive • San Jose, CA 95131 • USA • tel + 1 (408) 944-0800 • fax + 1 (408) 944-0970 • http://www.micrel.com
(1K Entries)
EEPROM /
Look Up
Interface
Engine
SCL
SDA
FIFO, Flow Control, VLAN and Priority Processing
Queue Priority
Management
Programming
Interface
1
LED
and
Features
• 8-port 10/100 integrated switch with 8 physical layer
• 32Kx32 of SRAM on chip for frame buffering
• 2.0Gbps high performance memory bandwidth
• 10BaseT and 100BaseTX modes of operation
• Superior analog technology for reduced power and die
• Single 2.0V power supply with options for 2.5V and 3.3V
• 900mA (1.80 W) including physical transmit drivers
• Supports port based VLAN
• Supports DiffServ priority, 802.1p based priority or port
• Indicators for link, activity, full/half-duplex and speed
• Unmanaged operation via strapping or EEPROM at
8-Port 10/100 Integrated Switch with PHY and Frame Buffer
Management
transceivers
size
I/O
based priority
system reset time
Buffer
LED[5][3,2,0]
LED[6][3,2,0]
LED[7][3,2,0]
LED[8][3,2,0]
LED[1][3,2,0]
LED[2][3,2,0]
LED[3][3,2,0]
LED[4][3,2,0]
SRAM
Buffers
KS8997
Rev. 1.07
KS8997
Micrel

Related parts for KSZ8997

KSZ8997 Summary of contents

Page 1

KS8997 General Description The KS8997 contains eight 10/100 physical layer transceiv- ers, eight MAC (Media Access Control) units with an inte- grated layer 2 switch. The device runs as an eight port integrated switch The KS8997 is designed to reside ...

Page 2

KS8997 Features (continued) • Hardware based 10/100, full/half, flow control and auto negotiation • Wire speed reception and transmission • Integrated address look-up engine, supports 1K absolute MAC addresses • Automatic address learning, address aging and address migration • Broadcast ...

Page 3

KS8997 Revision History Revision Date Summary of Changes 1.00 11/27/00 Document origination 1.01 04/02/01 Update maximum frame size Update EEPROM priority descriptions Update I/O descriptions Update Electrical Characteristics 1.02 05/11/01 Add MDI/MDI-X description 1.03 06/22/01 Change electrical requirements 1.04 06/25/01 ...

Page 4

KS8997 Table of Contents System Level Applications .............................................................................................................................................................. 6 Pin Description .............................................................................................................................................................................. 7 I/O Grouping ............................................................................................................................................................................ 10 I/O Descriptions ............................................................................................................................................................................ 11 Pin Configuration ........................................................................................................................................................................... 14 Functional Overview: Physical Layer Transceiver ..................................................................................................................... 15 100BaseTX Transmit ............................................................................................................................................................... 15 100BaseTX Receive ................................................................................................................................................................ 15 ...

Page 5

KS8997 Port 8 Control Register ................................................................................................................................................... 24 Reserved Register .......................................................................................................................................................... 24 Port 1 VLAN Mask Register ............................................................................................................................................ 25 Port 2 VLAN Mask Register ............................................................................................................................................ 25 Port 3 VLAN Mask Register ............................................................................................................................................ 25 Port 4 VLAN Mask Register ............................................................................................................................................ 26 Port ...

Page 6

KS8997 System Level Application The KS8997 can be configured to fit in an eight port 10/100 application. The major benefits of using the KS8997 are the lower power consumption, unmanaged operation, flexible KS8997 configuration, built in frame buffering, VLAN abilities ...

Page 7

KS8997 Pin Description Pin Number Pin Name Type 1 VDD_RX 2 GND_RX Gnd 3 GND_RX Gnd 4 VDD_RX 5 RXP[3] 6 RXM[3] 7 GND-ISO Gnd 8 TXP[3] 9 TXM[3] 10 GND_TX Gnd 11 VDD_TX 12 TXP[4] 13 TXM[4] 14 GND_TX ...

Page 8

KS8997 Pin Number Pin Name Type 39 GND-ISO Gnd 40 RXP[7] 41 RXM[7] 42 GND_TX Gnd 43 TXP[7] 44 TXM[7] 45 VDD_TX 46 VDD_TX 47 TXP[8] 48 TXM[8] 49 GND_TX Gnd 50 RXP[8] 51 RXM[8] 52 GND_RX Gnd 53 VDD_RX ...

Page 9

KS8997 Pin Number Pin Name Type 78 GND Gnd 79 LED[3][3] 80 LED[3][2] 81 LED[3][0] 82 LED[4][3] 83 LED[4][2] 84 LED[4][0] 85 VDD 86 GND Gnd 87 LED[5][3] 88 LED[5][2] 89 LED[5][0] 90 LED[6][3] 91 LED[6][2] 92 LED[6][0] 93 LED[7][3] ...

Page 10

KS8997 Pin Number Pin Name Type 117 RXM[1] 118 GND_TX Gnd 119 TXP[1] 120 TXM[1] 121 VDD_TX 122 VDD_TX 123 TXP[2] 124 TXM[2] 125 GND_TX Gnd 126 RXP[2] 127 RXM[2] 128 GND-ISO Gnd Note 1. Pwr = power supply Gnd ...

Page 11

KS8997 I/O Grouping Group Name Description PHY Physical Interface IND LED Indicators UP Unmanaged Programmable CTRL Control and Miscellaneous TEST Test (Factory) PWR/GND Power and Ground I/O Descriptions Group I/O Names Active Status PHY RXP[1:8] Analog RXM[1:8] TXP[1:8] Analog TXM[1:8] ...

Page 12

KS8997 Group I/O Names Active Status LED[2][0] LED[3][3] LED[3][2] LED[3][0] LED[4][3] LED[4][2] LED[4][0] LED[5][3] LED[5][2] LED[5][0] LED[6][3] LED[6][2] LED[6][0] LED[7][3] LED[7][2] LED[7][0] LED[8][3] LED[8][2] LED[8][0] CTRL EN1P H X1 Clock X2 Clock SCL Clock SDA RST# L Note 1. All ...

Page 13

KS8997 Group I/O Names Active Status TEST T[1], T[5] RLPBK H BIST H PWR/GND VDD_RX GND_RX VDD_TX GND_TX VDD_RCV GND_RCV VDD_PLLTX GND_PLLTX GND-ISO VDD VDD-IO GND Note 1. All unmanaged programming takes place at reset time only. For unmanaged programming: ...

Page 14

KS8997 Pin Configuration 103 MODESEL[1] MODESEL[0] T[ VDD_PLLTX GND_PLLTX VDD_RCV GND_RCV VDD_RCV GND_RCV VDD_RX GND_RX RXP[1] RXM[1] GND_TX TXP[1] TXM[1] VDD_TX VDD_TX TXP[2] TXM[2] GND_TX RXP[2] RXM[2] GND-ISO 1 KS8997 128-Pin PQFP (PQ) 14 Micrel 65 GND VDD ...

Page 15

KS8997 Functional Overview: Physical Layer Transceiver 100BaseTX Transmit The 100BaseTX transmit function performs parallel-to-serial conversion, 4B/5B coding, scrambling, NRZ to NRZI conversion, MLT3 encoding and transmission. The circuit starts with a parallel to serial conversion, which converts the MII data ...

Page 16

KS8997 Auto-Negotiation The KS8997 conforms to the auto-negotiation protocol as described by the 802.3 committee. Auto-negotiation allows UTP (Unshielded Twisted Pair) link partners to select the best common mode of operation. In auto-negotiation the link partners advertise capabilities across the ...

Page 17

KS8997 Functional Overview: Switch Core Address Look-Up The internal look-up table stores MAC addresses and their associated information. It contains 1K full CAM with 48-bit address plus switching information. The KS8997 is guaranteed to learn 1K addresses and distinguishes itself ...

Page 18

KS8997 Late Collision If a transmit packet experiences collisions after 512-bit times of the transmission, the packet will be dropped. Illegal Frames The KS8997 discards frames less than 64 bytes and can be programmed to accept frames up to 1536 ...

Page 19

KS8997 IPv4 DSCP Method This is another per frame way of determining outbound priority. The DSCP (Differentiated Services Code Point– RFC#2474) method uses the TOS field in the IP header to determine high and low priority on a per code ...

Page 20

KS8997 VLAN Operation The VLAN’s are setup by programming the VLAN Mask Registers in the “EEPROM Memory Map” section. The perspective of the VLAN is from the input port and which output ports it sees directly through the switch. For ...

Page 21

KS8997 EEPROM Operation The EEPROM interface utilizes 2 pins that provide a clock and a serial data path. As part of the initialization sequence, the KS8997 reads the contents of the EEPROM and loads the values into the appropriate registers. ...

Page 22

KS8997 Address Name Port 2 Control Register 5 7 Port 3 Control Register 6 7 ...

Page 23

KS8997 Address Name Port 4 Control Register 7 7 Port 5 Control Register 8 7 Port ...

Page 24

KS8997 Address Name Port 7 Control Register 10 7 Port 8 Control Register 11 7 ...

Page 25

KS8997 Address Name Port 1 VLAN Mask Register Port 2 VLAN Mask Register ...

Page 26

KS8997 Address Name Port 4 VLAN Mask Register Port 5 VLAN Mask ...

Page 27

KS8997 Address Name Port 6 VLAN Mask Register Port 7 VLAN Mask Register ...

Page 28

KS8997 Address Name Port 8 VLAN Mask Register Reserved Register 21 7-0 Port 1 VLAN Tag Insertion Value Registers 22 ...

Page 29

KS8997 Address Name 3-0 29 7-0 Port 5 VLAN Tag Insertion Value Registers 30 7 3-0 31 7-0 Port 6 VLAN Tag Insertion Value Registers 32 7 3-0 33 7-0 Port ...

Page 30

KS8997 Absolute Maximum Ratings Supply Voltage ( DD_RX DD_TX DD_RCV .............................................. –0.5V to +2.3V DD_PLLTX (V ) .................................................... –0.5V to +3.8V DDIO Input Voltage ............................................... –0.5V to +4.0V Output Voltage ...

Page 31

KS8997 Symbol Parameter 100BaseTX Transmit (measured differentially after 1:1 transformer) Duty Cycle Distortion Overshoot V Reference Voltage of ISET SET Output Jitters 10BaseT Receive V Squelch Threshold SQ 10BaseT Transmit (measured differentially after 1:1 transformer) V Peak Differential Output Voltage ...

Page 32

KS8997 Timing Diagrams SCL SDA Symbol Parameter t Clock Cycle CYC t Set-Up Time S t Hold Time H SCL SDA Symbol Parameter t Clock Cycle CYC t Set-Up Time OV KS8997 tcyc ts th Figure 2. EEPROM Input Timing ...

Page 33

KS8997 Reference Circuit See “I/O Description” section for pull-up/pull-down and float information. Reference circuits for unmanaged programming through LED ports Note: For brighter LED operation use VDD-IO = 3.3V August 2003 VDD-IO 220 Pull-Up 10k LED pin KS8997 VDD-IO 220 ...

Page 34

KS8997 4B/5B Coding In 100BaseTX and 100BaseFX the data and frame control are encoded in the transmitter (and decoded in the receiver) using a 4B/5B code. The extra code space is required to encode extra control (frame delineation) points. It ...

Page 35

KS8997 MLT3 Coding For 100BaseTX operation the NRZI (Non-Return to Zero Invert on ones) signal is line coded as MLT3. The net result of using MLT3 is to reduce the EMI (Electro Magnetic Interference) of the signal over twisted pair ...

Page 36

KS8997 Selection of Isolation Transformer One simple 1:1 isolation transformer is needed at the line interface. An isolation transformer with integrated common-mode choke is recommended for exceeding FCC requirements. The following table gives recommended transformer characteristics. Characteristics Name Turns Ratio ...

Page 37

KS8997 Package Information MICREL, INC. 1849 FORTUNE DRIVE SAN JOSE, CA 95131 USA + 1 (408) 944-0800 TEL The information furnished by Micrel in this datasheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel ...

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