AK4127VFP-E2 AKM Semiconductor Inc, AK4127VFP-E2 Datasheet

Page 1

High Performance Asynchronous SRC The AK4127 is a stereo digital sample rate converter (SRC). The input sample rate ranges from 8kHz to 216kHz. The output sample rate is from 8kHz to 216kHz. The system can take very ...

Page 2

GENERAL DESCRIPTION............................................................................................................................................... 1 FEATURES........................................................................................................................................................................ 1 ■ Ordering Guide ........................................................................................................................................................... 3 ■ Pin Layout ................................................................................................................................................................... 3 ■ Compatibility with AK4125........................................................................................................................................ 4 PIN/FUNCTION ................................................................................................................................................................ 5 ■ Handling of Unused pins............................................................................................................................................. 6 ABSOLUTE MAXIMUM RATINGS ............................................................................................................................... 6 RECOMMENDED OPERATING CONDITIONS ............................................................................................................ 6 SRC ...

Page 3

Ordering Guide −40 ∼ +85°C AK4127VF AKD4127 Evaluation Board for AK4127 ■ Pin Layout FILT AVSS PDN SMUTE DITHER PLL2 ILRCK IBICK SDTI IDIF0 IDIF1 IDIF2 PLL0 PLL1 UNLOCK MS0593-E-02 30pin VSOP (0.65mm pitch ...

Page 4

Compatibility with AK4125 Item TDM Mode Slave Mode at Bypass Mode OMCLK pin OMCLK=192fso for Output PORT (at Master Mode) MS0593-E-02 AK4125 AK4127 - - Normal Mode: OMCLK OMCLK TDM Mode: TDMIN X (-: Not available, X: Available) - ...

Page 5

No. Pin Name I/O 1 FILT O 2 AVSS - 3 PDN I 4 SMUTE I 5 DITHER I 6 PLL2 I 7 ILRCK I/O 8 IBICK I/O 9 SDTI I 10 IDIF0 I 11 IDIF1 I 12 IDIF2 I ...

Page 6

Handling of Unused pins The unused digital I/O pins should be processed appropriately as below. Classification Pin Name Analog FILT Digital SMUTE, DITHER IMCLK, OMCLK UNLOCK (AVSS=DVSS=0V; Note 1) Parameter Power Supplies: Analog Digital |AVSS − DVSS| Input Current, ...

Page 7

AVDD=DVDD=3.3V; AVSS=DVSS=0V; data = 24bit; measurement bandwidth = 20Hz ~ FSO/2; unless otherwise specified.) Parameter SRC Characteristics: Resolution Input Sample Rate Output Sample Rate THD+N (Input = 1kHz, 0dBFS, FSO/FSI = 44.1kHz/48kHz FSO/FSI = 48kHz/44.1kHz FSO/FSI = 48kHz/192kHz FSO/FSI ...

Page 8

AVDD=DVDD=3.0 ∼ 3.6V) Parameter Digital Filter Passband −0.01dB 0.985 ≤ FSO/FSI ≤ 6.000 0.905 ≤ FSO/FSI < 0.985 0.714 ≤ FSO/FSI < 0.905 0.656 ≤ FSO/FSI < 0.714 0.536 ≤ FSO/FSI < 0.656 0.492 ≤ FSO/FSI < 0.536 0.452 ...

Page 9

AVDD= DVDD=3.0 ∼ 3.6V) Parameter High-Level Input Voltage Low-Level Input Voltage High-Level Output Voltage Low-Level Output Voltage Input Leakage Current Power Supplies Power Supply Current Normal operation (PDN pin = “H”) FSI=FSO=48kHz at Slave Mode: FSI=FSO=192kHz at Master Mode: ...

Page 10

Input PORT (Master mode) IBICK Frequency IBICK Duty IBICK “↓” to ILRCK SDTI Hold Time from IBICK “↑” SDTI Setup Time to IBICK “↑” Output PORT (Slave mode) (8kHz ∼ 54kHz) OBICK Period (54kHz ∼ 108kHz) (108kHz ∼ 216kHz) OBICK ...

Page 11

Timing Diagram MCLK LRCK BICK LRCK tBLR BICK tLRS SDTO SDTI Note : BICK shows IBICK and OBICK, LRCK shows ILRCK and OLRCK. MS0593-E-02 1/fCLK tCLKH tCLKL 1/fs tBCK tBCKH tBCKL Clock Timing tLRB tBSD tSDS tSDH Audio Interface ...

Page 12

LRCK tMBLR BICK SDTO SDTI Note : BICK shows IBICK and OBICK, LRCK shows ILRCK and OLRCK. PDN MS0593-E-02 tBSD tSDS tSDH Audio Interface Timing (Master mode) tPD Power Down & Reset Timing - 12 - [AK4127] 50%DVDD dBCK 50%DVDD ...

Page 13

System Clock & Audio Interface Format for Input PORT The input port works in master mode or slave mode. An internal system clock is created by the internal PLL using ILRCK (Mode 0 ∼ IBICK ...

Page 14

ILRCK IBICK(32fs SDTI( IBICK(64fs) SDTI(i) Don't Care 15:MSB, 0:LSB ILRCK IBICK(64fs) SDTI(i) Don't Care 19:MSB, 0:LSB ILRCK IBICK(64fs SDTI(i) 23:MSB, 0:LSB ...

Page 15

ILRCK IBICK(64fs) Don't Care SDTI(i) 23:MSB, 0:LSB ■ System Clock & Audio Interface Format for Output PORT The output port works in master mode or slave mode. The MCLK is not needed in slave mode. The CMODE2-0 ...

Page 16

Mode Master / Slave OBIT1 0 L Slave 1 L CMODE2 “HLL” or “HHL” Master L Except 5 L CMODE2 “HLL” or “HHL” Table 5. Output Audio Interface Format ...

Page 17

OLRCK(I) OBICK (I: 256fso) TDMIN( SDTO( BICK OLRCK(I) OBICK (I: 256fso) TDMIN( SDTO( BICK MS0593-E-02 256 OBICK ...

Page 18

Cascade TDM Mode The AK4127 supports cascading connection four devices (8channels daisy chain configuration at TDM mode. In this mode, the SDTO pin of device #N is connected to TDMIN pin of device #(N+1). ...

Page 19

Soft Mute Operation 1. Manual mode Soft mute operation is performed in the digital domain of the SRC output. Soft mute can be controlled by the SMUTE pin. When the SMUTE pin changes to “H”, the SRC output data ...

Page 20

Dither The AK4127 has a dither circuit. The dither circuit adds the dither to the LSB of the output data, which is the value of the OBIT1-0 pins, by DITHER pin = “H” regardless of the SRC mode or ...

Page 21

Internal Reset Function for Clock Change The AK4127 is reset automatically when the output clock is stopped. If the output clock is started again, normal data is output within 100ms. ■ Sequence of Changing Clocks The change sequence of ...

Page 22

PLL Loop Filter The C1 and R should be connected in series and attached between the FILT pin and AVSS in parallel with C2. Please be careful the noise onto the FILT pin. When using IBICK, the value of ...

Page 23

Figure 19 and Figure 20 show the system connection diagrams. The evaluation board demonstrates application circuits, the optimum layout, power supply arrangements and measurement results. • Input PORT: Slave Mode, IBICK lock mode (64fsi), 24bit MSB justified • Output PORT: ...

Page 24

Input PORT: Slave Mode, IBICK lock mode (64fsi), 24bit MSB justified • Output PORT: Master mode, 24bit MSB justified • Dither = OFF 470 1.0n 0.22μ Reset fsi 64fsi DSP, uP Note: - AVSS and DVSS of the AK4127 ...

Page 25

Jitter Tolerance Figure 21 shows the jitter tolerance to ILRCK and IBICK. The jitter quantity is defined by the jitter frequency and the jitter amplitude shown in Figure 21. When the jitter amplitude is 0.01Uipp or less, the AK4127 ...

Page 26

Digital Filter Response Example Table 8 shows the examples of digital filter response performed by the AK4127. Ratio FSO/FSI [kHz] 4.000 192/48.0 1.000 48.0/48.0 0.919 44.1/48.0 0.725 32.0/44.1 0.667 32.0/48.0 0.544 48.0/88.2 0.500 48.0/96.0 0.500 44.1/88.2 0.459 44.1/96.0 0.363 ...

Page 27

VSOP (Unit: mm) *9.7 ± 0.1 0 0.22 ± 0.1 0.12 M NOTE: Dimension "*" does not include mold flash. ■ Material & Lead finish Package molding compound: Lead frame material: Lead frame surface treatment: MS0593-E-02 PACKAGE ...

Page 28

XXXB: Lot number (X: Digit number, B: Alpha character) YYYYC: Assembly date (Y: Digit number, C: Alpha character) Date (YY/MM/DD) Revision 07/02/07 00 07/07/26 01 10/05/17 02 MS0593-E-02 MARKING AKM AK4127VF XXXBYYYYC XXXBYYYYC Date code identifier REVISION HISTORY Reason Page ...

Page 29

These products and their specifications are subject to change without notice. When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei Microdevices Corporation (AKM) or authorized distributors as to current status ...