MT9P401I12STC Aptina LLC, MT9P401I12STC Datasheet - Page 27

• Manufacturer Part Number: MT9P401I12STC
• Description: SENSOR IMAGE CMOS 5MP 48LCC
• Manufacturer: Aptina LLC
• Type: CMOS Imagingr
• Series: DigitalClarity®r

Specifications of MT9P401I12STC

• Pixel Size: 2.2µm x 2.2µm
• Active Pixel Array: 2592H x 1944V
• Frames Per Second: 60
• Voltage - Supply: 2.6 V ~ 3.1 V
• Package / Case: 48-iLCC
• Sensor Image Color Type: Monochrome
• Sensor Image Size: 2592x1944Pixels
• Operating Supply Voltage (typ): 1.8/2.8V
• Operating Supply Voltage (max): 3.1V
• Operating Temp Range: -30C to 70C
• Package Type: ILCC
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 557-1263; MT9P401I12STC; Q3412742

Table 13:
PDF: 09005aef82acb06f/Source: 09005aef81a4a477
MT9P401_DS_2 - Rev. B 9/07 EN
R0x00A
R0x00B
R0x00C
Reg. #
R10:0
R11:0
R12:0
A negative adjustment to the effective shutter width in ACLKs. See Shutter_Width_Lower. Writes are
synchronized to frame boundaries. Affected by Synchronize_Changes. Legal values: [0, 8191].
14:11
15:0
15:0
15:0
Bits
10:8
15:3
6:0
Register Description (continued)
15
7
2
1
0
Default
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
X
X
X
Name
Pixel Clock Control (RW)
Invert Pixel Clock
When set, LV, FV, and D_OUT should be captured on the rising edge of PIXCLK. When clear,
they should be captured on the falling edge. This is accomplished by inverting the PIXCLK
output.
NOTE: This field is not reset by the soft Reset (R13).
Reserved
Shift Pixel Clock
Two's complement value representing how far to shift the PIXCLK output pin relative to
D
relative to the internal array/datapath clock). No effect unless PIXCLK is divided by Divide
Pixel Clock.
NOTE: This field is not reset by the soft Reset (R13).
Legal values: [-2, 2].
Reserved
Divide Pixel Clock
Produces a PIXCLK that is divided by the value times two. The value must be zero or a
power of 2. This will slow down the internal clock in the array control and datapath blocks,
including pixel readout. It will not affect the two-wire serial interface clock. A value of “0”
corresponds to a PIXCLK with the same frequency as EXTCLK. A value of 1 means f_PIXCLK
= (f_EXTCLK / 2); 2 means f_PIXCLK = (f_EXTCLK / 4); 64 means f_PIXCLK = (f_EXTCLK / 128);
and so on.
NOTE: This field is not reset by the soft Reset (R13). This field should not be written while in
streaming mode. Instead, Pause_Restart should be used to suspend output while the
divider is being changed. Legal values: [0, 1, 2, 4, 8, 16, 32, 64].
Restart (RW)
Reserved
Trigger
Setting this bit in Snapshot mode will cause the next trigger to occur as if the TRIGGER pin
were properly asserted/negated. Ineffective if not in Snapshot mode. The sense of this bit is
NOT affected by Invert Trigger.
When using this bit instead of the TRIGGER pin, make sure that either the trigger pin is
continuously asserted, or that the pad is continuously negated and Invert_Trigger is set.
Pause Restart
When set, Restart will not automatically be cleared. Instead, the sensor will pause at row 0
after Restart is set. When Pause_Restart is cleared, the sensor will resume. This allows for a
repeatable delay from clearing restart to FV. When clearing this bit, be sure not to clear
Restart as well: it will be cleared automatically when the device has restarted.
Restart
Setting this bit will cause the sensor to abandon the current frame and restart from the
first row. It will take up to 2 * t_ROW for the restart to take effect. This bit resets to 0
automatically unless Pause_Restart is set. Manually setting this bit to zero will cause
undefined behavior.
Volatile.
Shutter Delay (RW)
OUT
, in EXTCLK cycles. Positive values shift PIXCLK later in time relative to D
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MT9P401: 1/2.5-Inch 5Mp Digital Image Sensor
27
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©2007 Micron Technology, Inc. All rights reserved.
OUT
Registers
(and thus