CYII4SM014KAA-GECU Cypress Semiconductor Corp, CYII4SM014KAA-GECU Datasheet - Page 10

• Manufacturer Part Number: CYII4SM014KAA-GECU
• Description: IC IMAGE SENSOR 14MP CMOS 49-PGA
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYII4SM014KAA-GECU

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 7
the clocking scheme.
Table 3. Timing Constraints for the Row Sequencer
Notes CLK = one clock period of the master clock, shortest system time period available.
Document #: 38-05709 Rev. *F
Symbol
m
a
b
c
d
e
g
h
k
f
i
j
l
shows the basic timing diagram of the IBIS4-14000 image sensor and
CLOCK_YL
SYNC_YR
SYNC_YL
SELECT
RESET
h+2*CLK
SHR
SHS
SYR
SYL
PC
Min
200
–
–
–
–
–
–
–
–
–
–
–
a
1.28
Typ
600
100
500
240
500
2.7
1.3
6.5
1.4
k
10
5
3
Optional reset pulse
l
for reset black
h
b
Units
 s
 s
 s
 s
 s
 s
 s
 s
ns
ns
ns
ns
ns
d
c
e
Min. SYNC set-up times. SYNC_Y is clocked in on rising edge on CLK_Y. SYNC_Y pulse
must overlap CLK_Y by one clock period. Setup times of 200 ns apply after SYNC edges.
Within this setup time no rising CLK edge may occur.
Duration of PC pulse.
Delay between falling edge on PC and rising edge on SHS/SHR. Duration of SHS/SHR
pulse.
Delay between rising edge on PC and rising edge on SELECT.
Delay between rising edge on SELECT and rising edge on SHS/SHR.
Delay between rising edge on SHS and falling edge on SELECT.
Delay between falling edge of SELECT and rising edge of RESET.
Duration of RESET pulse.
Delay between rising edge on SHR and rising edge on SYR.
SYL and SYR pulses must overlap second RESET pulse at both sides by one clock cycle.
Duration of CLOCK_Y pulse.
Delay between falling edge of CLK_Y and Falling edge of PC and SHS.
Delay between falling edge of RESET and falling edge of PC and SHR.
f
Figure 7. Line Read Out Timing
g
h
m
b
c
d
e
Table 3
f
Description
i
on page 10 shows the timing specifications of
Only when the electronic
j
shutter is used
h
j
CYII4SM014KAA
Once each
For each
new row
frame
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