CYII4SM014KAA-GECU Cypress Semiconductor Corp, CYII4SM014KAA-GECU Datasheet - Page 15

• Manufacturer Part Number: CYII4SM014KAA-GECU
• Description: IC IMAGE SENSOR 14MP CMOS 49-PGA
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYII4SM014KAA-GECU

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Package Information
Pin Configuration
Table 7
Table 7. Pinout Configuration
Document #: 38-05709 Rev. *F
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Pin #
lists the pin configuration of the IBIS4-14000.
OBIAS
GND
OUT3
GND
OUT4
VDD
GND
OUT2
GND
OUT1
GND
DARKREF
TEMP1
PHDIODE
CLK_Y
SYNC_Y
TEMP2
GNDAB
GND
VDD
VDDR
CLK_YR
SYR
SYNC_YR
VDDARRAY Pixel array power supply (= pin 26)
VDDARRAY Pixel array power supply (= pin 25)
SYNC_YL
SYL
Name
Bias current output amplifiers
Ground for output 3
Output 3
Ground for output 4
Output 4
Power supply
Ground
Output 2
Ground for output 2
Output 1
Ground for output 1
Offset level of output signal
Temperature sensor.
Located near the output amplifiers (pixel
4536, 0) near the stitch line)
Photodiode output.
Yields the equivalent photocurrent of 250 x
50 pixels. Diode is located right under the
pad
Y clock for switchboard
Y SYNC pulse for switchboard
Temperature sensor
Located near pixel (24,0)
Anti-blooming reference level (= pin 33)
Ground
Power supply
Power supply for reset line drivers
Clock of YR shift register
Activate YR shift register for driving of reset
and select line of pixel array
Sets the YR shift register to row 1
Sets the YL shift register to row 1
Activate YL shift register for driving of reset
and select line of pixel array
Function
Figure 12
on page 18 shows the assignment of pin numbers on the package.
Connect with 10 k  to V
Nominal 3.3 V
0 V
Typ. 2.6 V. min. 1.7 V max. 3 V
Any voltage above GND forward biases the diode.
Connect to GND if not used
Reverse biased by any voltage above GND
Connect to GND if not used.
Clocks on rising edge
Connect to CLK_YL (or drive identically)
Low active: synchronous sync on rising edge of CLK_Y
Connect to SYNC_YL (or drive identically)
Any voltage above GND forward biases the diode
Connect to GND if not used
Typ. 0 V. Set to 1.5 V for improved anti-blooming
0 V
Nominal 3.3 V
Nominal 4 V
Connected on-chip to pin 30
Shifts on rising edge
High active. Exact pulsing pattern see timing diagram.
Both SYR = 1 and SYL = 1 is not allowed, except when the
same row is selected
Low active. Synchronous sync on rising edge of CLK_YR
200 ns setup time
3 V
3 V
Low active. Synchronous sync on rising edge of CLK_YL
200 ns setup time
High active. Exact pulsing pattern see timing diagram.
Both SYR = 1 and SYL = 1 is not allowed, except when the
same row is selected
DD
Comment
and decouple with 100 nF to GND
CYII4SM014KAA
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