LTC3703IGN-5 Linear Technology, LTC3703IGN-5 Datasheet - Page 26

• Manufacturer Part Number: LTC3703IGN-5
• Description: IC,SMPS CONTROLLER,VOLTAGE-MODE,CMOS,SSOP,16PIN,PLASTIC
• Manufacturer: Linear Technology

LTC3703
APPLICATIO S I FOR ATIO
3. I
MOSFETs, the inductor and input and output capacitor
ESR. In continuous mode, the average output current
flows through L but is “chopped” between the topside
MOSFET and the synchronous MOSFET. If the two
MOSFETs have approximately the same R
resistance of one MOSFET can simply be summed with the
DCR resistance of L to obtain I
each R
tance is 50mΩ. This results in losses ranging from 1% to
5% as the output current increases from 1A to 5A for a 5V
output.
4. Transition losses apply only to the topside MOSFET in
buck mode and they become significant when operating at
higher input voltages (typically 20V or greater). Transition
losses can be estimated from the second term of the P
equation found in the Power MOSFET Selection section.
The transition losses can become very significant at the
high end of the LTC3703 operating voltage range. To
improve efficiency, one may consider lowering the fre-
quency and/or using MOSFETs with lower C
expense of higher R
Other losses including C
losses, Schottky conduction losses during dead-time, and
inductor core losses generally account for less than 2%
total additional loss.
Transient Response
Due to the high gain error amplifier and line feedforward
compensation of the LTC3703, the output accuracy due to
DC variations in input voltage and output load current will
be almost negligible. For the few cycles following a load
transient, however, the output deviation may be larger
while the feedback loop is responding. Consider a typical
48V input to 5V output application circuit, subjected to a
1A to 5A load transient. Initially, the loop is in regulation
and the DC current in the output capacitor is zero. Sud-
denly, an extra 4A (= 5A-1A) flows out of the output
capacitor while the inductor is still supplying only 1A. This
sudden change will generate a (4A) • (R
at the output; with a typical 0.015Ω output capacitor ESR,
this is a 60mV step at the output.
26
2
R losses are predicted from the DC resistances of
DS(ON)
= 25mΩ and R
U
DS(ON)
U
IN
.
L
and C
2
= 25mΩ, then total resis-
R losses. For example, if
W
OUT
ESR
ESR dissipative
DS(ON)
) voltage step
RSS
U
, then the
at the
MAIN
The feedback loop will respond and will move at the band-
width allowed by the external compensation network
towards a new duty cycle. If the unity gain crossover fre-
quency is set to 50kHz, the COMP pin will get to 60% of the
way to 90% duty cycle in 3µs. Now the inductor is seeing
43V across itself for a large portion of the cycle and its
current will increase from 1A at a rate set by di/dt = V/L. If
the inductor value is 10µH, the peak di/dt will be 43V/10µH
or 4.3A/µs. Sometime in the next few micro-seconds after
the switch cycle begins, the inductor current will have
risen to the 5A level of the load current and the output
voltage will stop dropping. At this point, the inductor cur-
rent will rise somewhat above the level of the output cur-
rent to replenish the charge lost from the output capacitor
during the load transient. With a properly compensated
loop, the entire recovery time will be inside of 10µs.
Most loads care only about the maximum deviation from
ideal, which occurs somewhere in the first two cycles after
the load step hits. During this time, the output capacitor
does all the work until the inductor and control loop regain
control. The initial drop (or rise if the load steps down) is
entirely controlled by the ESR of the capacitor and amounts
to most of the total voltage drop. To minimize this drop,
choose a low ESR capacitor and/or parallel multiple ca-
pacitors at the output. The capacitance value accounts for
the rest of the voltage drop until the inductor current rises.
With most output capacitors, several devices paralleled to
get the ESR down will have so much capacitance that this
drop term is negligible. Ceramic capacitors are an excep-
tion; a small ceramic capacitor can have suitably low ESR
with relatively small values of capacitance, making this
second drop term more significant.
Optimizing Loop Compensation
Loop compensation has a fundamental impact on tran-
sient recovery time, the time it takes the LTC3703 to
recover after the output voltage has dropped due to a load
step. Optimizing loop compensation entails maintaining
the highest possible loop bandwidth while ensuring loop
stability. The feedback component selection section de-
scribes in detail the techniques used to design an opti-
mized Type 3 feedback loop, appropriate for most LTC3703
systems.
3703fa