LTC3703IGN-5 Linear Technology, LTC3703IGN-5 Datasheet - Page 28

• Manufacturer Part Number: LTC3703IGN-5
• Description: IC,SMPS CONTROLLER,VOLTAGE-MODE,CMOS,SSOP,16PIN,PLASTIC
• Manufacturer: Linear Technology

LTC3703
APPLICATIO S I FOR ATIO
And double check the assumed T
Since the synchronous MOSFET will be conducting over
twice as long each period (almost 100% of the period in
short circuit) as the top MOSFET, use two Si7456DP
MOSFETs on the bottom:
Next, set the current limit resistor. Since I
limit should be set such that the minimum current limit is
>10A. Minimum current limit occurs at maximum R
Using the above calculation for bottom MOSFET T
max R
Therefore, I
= 0.215V. The R
0.215V/12µA = 18kΩ.
C
2) at 85°C. For the output capacitor, two low ESR OSCON
capacitors (18mΩ each) are used to minimize output
voltage changes due to inductor current ripple and load
steps. The ripple voltage will be:
However, a 0A to 10A load step will cause an output
voltage change of up to:
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC3703. These items are also illustrated graphically in
the layout diagram of Figure 18. For layout of a Boost Mode
Converter, layout is similar with V
Check the following in your layout:
28
IN
T
T
∆V
= 36mV
∆V
P
= 90mV
is chosen for an RMS current rating of about 5A (I
J
SYNC
J
= 70°C + (1.64W)(20°C/W) = 103°C
= 70°C + (1.74W)(20°C/W) = 105°C
OUT(RIPPLE)
OUT(STEP)
DS(ON)
=
⎛
⎜
⎝
MAX
⎛
⎜
⎝
0 025
= (25mΩ/2) [1 + 0.009 (105-25)] = 21.5mΩ
72 12
.
2
pin voltage should be set to (10A)(0.0215)
= ∆I
72
−
SET
= ∆I
⎞
⎟ =
⎠
U
LOAD(ESR)
⎞
⎟
⎠
resistor can now be chosen to be
L(MAX)
( )
1 74
10 1 0 009 100 25
.
U
2
[
W
(ESR) = (4A)(0.018Ω/2)
+
= (10A)(0.009Ω)
.
J
IN
in the MOSFET:
W
and V
(
MAX
–
OUT
= 10A, the
U
swapped.
) •
]
DS(ON)
J
, the
MAX
.
/
1. Keep the signal and power grounds separate. The signal
ground consists of the LTC3703 GND pin, the ground
return of C
ground consists of the Schottky diode anode, the source
of the bottom side MOSFET, and the (–) terminal of the
input capacitor and DRV
and power grounds together at the (–) terminal of the
output capacitor. Also, try to connect the (–) terminal of
the output capacitor as close as possible to the (–)
terminals of the input and DRV
the Schottky loop described in (2).
2. The high di/dt loop formed by the top N-channel
MOSFET, the bottom MOSFET and the C
should have short leads and PC trace lengths to minimize
high frequency noise and voltage stress from inductive
ringing.
3. Connect the drain of the top side MOSFET directly to the
(+) plate of C
MOSFET directly to the (–) terminal of C
provides the AC current to the MOSFETs.
4. Place the ceramic C
diately next to the IC, between DRV
capacitor carries the MOSFET drivers’ current peaks.
Likewise the C
between BOOST and SW.
5. Place the small-signal components away from high
frequency switching nodes (BOOST, SW, TG, and BG). In
the layout shown in Figure 20, all the small signal compo-
nents have been placed on one side of the IC and all of the
power components have been placed on the other. This
also helps keep the signal ground and power ground
isolated.
6. A separate decoupling capacitor for the supply, V
useful with an RC filter between the DRV
pin to filter any noise injected by the drivers. Connect this
capacitor close to the IC, between the V
and keep the ground side of the V
ground) isolated from the ground side of the DRV
capacitor (power ground).
7. For optimum load regulation and true remote sensing,
the top of the output resistor divider should connect
independently to the top of the output capacitor (Kelvin
VCC
IN
, and the (–) terminal of V
, and connect the source of the bottom side
B
capacitor should also be next to the IC
DRVCC
CC
capacitor. Connect the signal
decoupling capacitor imme-
CC
capacitor and away from
CC
CC
and BGRTN. This
CC
IN
capacitor (signal
CC
OUT
. This capacitor
supply and V
and GND pins
IN
. The power
capacitor
CC
3703fa
, is
CC
CC