FDG6322C Fairchild Semiconductor, FDG6322C Datasheet

IC FET DGTL N/P-CHAN DUAL SC70-6

FDG6322C

Manufacturer Part Number
FDG6322C
Description
IC FET DGTL N/P-CHAN DUAL SC70-6
Manufacturer
Fairchild Semiconductor
Datasheet

Specifications of FDG6322C

Fet Type
N and P-Channel
Fet Feature
Logic Level Gate
Rds On (max) @ Id, Vgs
4 Ohm @ 220mA, 4.5V
Drain To Source Voltage (vdss)
25V
Current - Continuous Drain (id) @ 25° C
220mA, 410mA
Vgs(th) (max) @ Id
1.5V @ 250µA
Gate Charge (qg) @ Vgs
0.4nC @ 4.5V
Input Capacitance (ciss) @ Vds
9.5pF @ 10V
Power - Max
300mW
Mounting Type
Surface Mount
Package / Case
SC-70-6, SC-88, SOT-363
Configuration
Dual
Transistor Polarity
N and P-Channel
Resistance Drain-source Rds (on)
4 Ohm @ 4.5 V @ N Channel
Forward Transconductance Gfs (max / Min)
0.2 S, 0.9 S
Drain-source Breakdown Voltage
25 V
Gate-source Breakdown Voltage
8 V
Continuous Drain Current
0.22 A @ N Channel or 0.41 A @ P Channel
Power Dissipation
300 mW
Maximum Operating Temperature
+ 150 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 55 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
FDG6322CTR

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© 2008 Fairchild Semiconductor Corporation
These dual N & P-Channel logic level enhancement mode
field effect transistors are produced using Fairchild's
proprietary, high cell density, DMOS technology. This very
high density process is especially tailored to minimize
on-state resistance.
especially for low voltage applications as a replacement for
bipolar digital transistors and small signal MOSFETs. Since
bias resistors are not required, this dual digital FET can
replace several different digital transistors, with different bias
resistor values.
FDG6322C
Dual N & P Channel Digital FET
General Description
Symbol
V
V
I
P
T
ESD
THERMAL CHARACTERISTICS
R
D
Absolute Maximum Ratings
J
DS
GSS
D
,T
JA
S
STG
SC70-6
Parameter
Drain-Source Voltage
Gate-Source Voltage
Drain Current
Maximum Power Dissipation
Operating and Storage Temperature Range
Electrostatic Discharge Rating MIL-STD-883D
Human Body Model (100pf / 1500 Ohm)
Thermal Resistance, Junction-to-Ambient
Mark: .22
SC70-6
D1
This
pin 1
G2
- Continuous
- Pulsed
SOT-23
S2
device has been designed
S1
G1
T
A
= 25
D2
SuperSOT
o
C unless other wise noted
(Note 1)
(Note1)
TM
-6
Features
SOT-8
N-Channel
N-Ch 0.22 A, 25 V, R
P-Ch -0.41 A,-25V, R
Very small package outline SC70-6.
Very low level gate drive requirements allowing direct
operation in 3 V circuits (V
Gate-Source Zener for ESD ruggedness
(>6kV Human Body Model).
0.22
0.65
25
8
-55 to 150
R
R
415
0.3
DS(ON)
6
DS(ON)
DS(ON)
DS(ON)
SO-8
= 1.5
= 5.0
June 2008
= 4.0
GS(th)
= 1.1
P-Channel
Q1
Q2
-0.41
-1.2
-25
< 1.5 V).
@ V
-8
@ V
6 6
4
@ V
@ V
GS
GS
= -2.7V.
= 2.7 V.
GS
GS
= 4.5 V,
= -4.5V,
SOIC-14
FDG6322C Rev.F1
Units
°C/W
kV
W
°C
V
V
A

Related parts for FDG6322C

FDG6322C Summary of contents

Page 1

... Human Body Model). TM SOT-8 SuperSOT - unless other wise noted A N-Channel 25 0.22 0.65 (Note 1) (Note1) June 2008 = 4 4.5 V, DS(ON 5 2.7 V. DS(ON 1 -4.5V, DS(ON 1 -2.7V. DS(ON) GS < 1.5 V). GS(th) SO-8 SOIC- P-Channel - -0.41 -1.2 0.3 -55 to 150 6 415 Units °C kV °C/W FDG6322C Rev.F1 ...

Page 2

... C N-Ch -2 P-Ch 2.1 N-Ch 2.6 4 =125°C 5 3.7 5 P-Ch 0.85 1.1 =125°C 1.2 1.9 J 1.15 1.5 N-Ch 0.22 P-Ch -0.41 N-Ch 0.2 P-Ch 0.9 N-Ch 9.5 P-Ch 62 N-Ch 6 P-Ch 34 N-Ch 1.3 P-Ch 10 FDG6322C Rev.F1 Units V o mV/ C µA µ mV ...

Page 3

... C/W on minimum mounting pad on FR-4 board in still air. JA Type Min Typ Max Units N- P- N- N- N-Ch 0.29 0.4 nC P-Ch 1.1 1.5 N-Ch 0.12 nC P-Ch 0.31 N-Ch 0.03 nC P-Ch 0.29 N-Ch 0.25 A P-Ch -0.25 N-Ch 0.8 1.2 V P-Ch -0.85 -1.2 is guaranteed JC FDG6322C Rev.F1 ...

Page 4

... Figure 2. On-Resistance Variation with Drain Current and Gate Voltage 0.10A D T =125°C A 25° ,GATE TO SOURCE VOLTAGE (V) GS Gate-to-Source Voltage 125°C J 25°C -55°C 0 0.2 0.4 0.6 0 BODY DIODE FORWARD VOLTAGE (V) SD Variation with Source Current and Temperature. FDG6322C.Rev F1 5.0V 0.4 5 1.2 ...

Page 5

... Figure 9. Maximum Safe Operating Area. (continued MHz 0.1 0.5 0.6 Figure 8. Capacitance Characteristics 0.0001 Figure 10. Single Pulse Maximum Power C iss C oss C rss = DRAIN TO SOURCE VOLTAGE (V) DS SINGLE PULSE R =415°C 25°C A 0.001 0.01 0 SINGLE PULSE TIME (SEC) Dissipation. FDG6322C Rev.F1 25 200 ...

Page 6

... DRAIN CURRENT (A) D Drain Current and Gate Voltage -0. 125 ° GATE TO SOURCE VOLTAGE (V) GS Gate-to-Source Voltage 125°C J 25°C -55°C 0.2 0.4 0.6 0 BODY DIODE FORWARD VOLTAGE (V) SD Variation with Source Current and Temperature. -4.5V 1 1.2 25° 1.2 FDG6322C Rev.F1 ...

Page 7

... Figure 19. Maximum Safe Operating Area. (continued) 200 -10V 80 -15V 0.1 1.2 1.6 Figure 18. Capacitance Characteristics 0.0001 Figure 20. Single Pulse Maximum Power C iss C oss C rss MHz 0 DRAIN TO SOURCE VOLTAGE (V) DS SINGLE PULSE R =415°C 25°C A 0.001 0.01 0 SINGLE PULSE TIME (SEC) Dissipation. FDG6322C Rev.F1 25 200 ...

Page 8

... Figure 21. Transient Thermal Response Curve. Thermal characterization performed using the conditions described in note 1. Transient thermalresponse will change depending on the circuit board design. (continued) 0.01 0 TIME (sec ( =415 °C/W JA P(pk ( Duty Cycle 100 200 FDG6322C Rev.F1 ...

Page 9

... TRADEMARKS The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global subsidiaries, and is not intended exhaustive list of all such trademarks. ® ACEx Build it Now™ CorePLUS™ CorePOWER™ CROSSVOLT™ CTL™ Current Transfer Logic™ ...

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