FDS6912 Fairchild Semiconductor, FDS6912 Datasheet - Page 2

MOSFET N-CH DUAL PWM OPT 8-SOIC

FDS6912

Manufacturer Part Number
FDS6912
Description
MOSFET N-CH DUAL PWM OPT 8-SOIC
Manufacturer
Fairchild Semiconductor
Series
PowerTrench®r
Datasheets

Specifications of FDS6912

Fet Type
2 N-Channel (Dual)
Fet Feature
Logic Level Gate
Rds On (max) @ Id, Vgs
28 mOhm @ 6A, 10V
Drain To Source Voltage (vdss)
30V
Current - Continuous Drain (id) @ 25° C
6A
Vgs(th) (max) @ Id
3V @ 250µA
Gate Charge (qg) @ Vgs
10nC @ 5V
Input Capacitance (ciss) @ Vds
740pF @ 15V
Power - Max
900mW
Mounting Type
Surface Mount
Package / Case
8-SOIC (3.9mm Width)
Module Configuration
Dual
Transistor Polarity
N Channel
Continuous Drain Current Id
6A
Drain Source Voltage Vds
30V
On Resistance Rds(on)
28mohm
Rds(on) Test Voltage Vgs
10V
Rohs Compliant
Yes
Dc
0452
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Notes:
1. R
Scale 1 : 1 on letter size paper
Pulse Test: Pulse Width < 300 s, Duty Cycle < 2.0%
Electrical Characteristics
Symbol
Off Characteristics
BV
I
I
On Characteristics
V
R
I
g
Dynamic Characteristics
C
C
C
R
Switching Characteristics
t
t
t
t
Q
Q
Q
Drain–Source Diode Characteristics and Maximum Ratings
I
V
t
Q
the drain pins. R
DSS
GSS
D(on)
d(on)
r
d(off)
f
S
rr
FS
BV
V
GS(th)
SD
DS(on)
iss
oss
rss
G
g
gs
gd
rr
JA
GS(th)
DSS
T
T
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of
DSS
J
J
Drain–Source Breakdown Voltage
Breakdown Voltage Temperature
Coefficient
Zero Gate Voltage Drain Current
Gate–Source Leakage
Gate Threshold Voltage
Gate Threshold Voltage
Temperature Coefficient
Static Drain–Source
On–Resistance
On–State Drain Current
Forward Transconductance
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Gate Resistance
Turn–On Delay Time
Turn–On Rise Time
Turn–Off Delay Time
Turn–Off Fall Time
Total Gate Charge
Gate–Source Charge
Gate–Drain Charge
Maximum Continuous Drain–Source Diode Forward Current
Drain–Source Diode Forward
Voltage
Diode Reverse Recovery Time
Diode Reverse Recovery Charge
JC
is guaranteed by design while R
a) 78°C/W when
mounted on a 0.5in
pad of 2 oz copper
Parameter
(Note 2)
2
(Note 2)
CA
is determined by the user's board design.
T
V
I
V
V
V
V
I
V
V
V
V
V
V
f = 1.0 MHz
V
V
V
V
V
V
I
A
D
D
F
b) 125°C/W when
= 25°C unless otherwise noted
GS
DS
DS
GS
DS
GS
GS
GS
GS
DS
DS
GS
DD
GS
DS
GS
GS
= 6 A,
= 250 A, Referenced to 25 C
= 250 A, Referenced to 25 C
mounted on a 0.02
in
copper
= 24 V,
= 24 V, V
= 20 V, V
= V
= 10 V,
= 15 V,
= 15 V,
= 0 V,
= 10 V,
= 4.5 V, I
= 10 V, I
= 10 V,
= 15 mV, f = 1.0 MHz
= 15 V,
= 10 V,
= 5 V
= 0 V,
2
pad of 2 oz
Test Conditions
GS
,
D
I
d
GS
S
I
V
I
I
V
I
V
I
R
I
iF
= 6 A,T
D
D
D
D
D
D
D
= 1.3 A
/d
GS
DS
DS
GEN
= 0 V, T
GS
= 250 A
= 250 A
= 6 A
= 5 A
= 6 A
= 1 A,
= 6 A,
t
= 0 V
= 5 V
= 100 A/µs
= 0 V
= 0 V,
= 6
J
= 125 C
J
= 55 C
(Note 2)
Min
20
30
1
c) 135°C/W when mounted on a
minimum mounting pad.
Typ Max Units
–4.5
0.75
575
145
1.9
2.1
5.8
1.7
2.1
25
19
24
27
25
65
23
20
10
8
5
3
8.1
1.3
1.2
10
100
28
35
44
16
10
37
1
3
6
FDS6912A Rev D(W)
mV/ C
mV/ C
m
nC
nC
nC
nC
nA
pF
pF
pF
nS
ns
ns
ns
ns
V
V
A
S
A
V
A

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