MMDF1N05ER2G ON Semiconductor, MMDF1N05ER2G Datasheet - Page 4

• Manufacturer Part Number: MMDF1N05ER2G
• Description: MOSFET N-CHAN DUAL 2A 50V 8SOIC
• Manufacturer: ON Semiconductor

Specifications of MMDF1N05ER2G

• Fet Type: 2 N-Channel (Dual)
• Fet Feature: Logic Level Gate
• Rds On (max) @ Id, Vgs: 300 mOhm @ 1.5A, 10V
• Drain To Source Voltage (vdss): 50V
• Current - Continuous Drain (id) @ 25° C: 2A
• Vgs(th) (max) @ Id: 3V @ 250µA
• Gate Charge (qg) @ Vgs: 12.5nC @ 10V
• Input Capacitance (ciss) @ Vds: 330pF @ 25V
• Power - Max: 2W
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Module Configuration: Dual
• Transistor Polarity: N Channel
• Continuous Drain Current Id: 2A
• Drain Source Voltage Vds: 50V
• On Resistance Rds(on): 300mohm
• Rds(on) Test Voltage Vgs: 10V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: MMDF1N05ER2GOS

SAFE OPERATING AREA INFORMATION
Forward Biased Safe Operating Area
voltage and drain current that a device can safely handle
when it is forward biased, or when it is on, or being turned
on. Because these curves include the limitations of
simultaneous high voltage and high current, up to the rating
of the device, they are especially useful to designers of linear
systems. The curves are based on a case temperature of 25°C
and a maximum junction temperature of 150°C. Limitations
for repetitive pulses at various case temperatures can be
determined by using the thermal response curves. ON
Semiconductor Application Note, AN569, “Transient
Thermal Resistance − General Data and Its Use” provides
detailed instructions.
The FBSOA curves define the maximum drain−to−source
1200
1000
800
600
400
200
0
0.001
20
0.01
0.1
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
10
1.0E−05
1
15
V
Figure 7. Capacitance Variation
DS
C
C
D = 0.5
0.02
0.05
10
0.01
0.1
SINGLE PULSE
iss
rss
0.2
= 0
V
GS
1.0E−04
5
0
0
5
1.0E−03
V
V
GS
DS
10
= 0
C
C
C
rss
15
oss
iss
1.0E−02
Figure 10. Thermal Response
T
J
= 25°C
20
http://onsemi.com
MMDF1N05E
25
t, TIME (s)
Chip
4
1.0E−01
0.01
0.0175 W
12
10
0.0154 F
100
0.1
8
6
4
2
0
10
1
0
0.1
V
SINGLE PULSE
T
Figure 9. Maximum Rated Forward Biased
C
GS
= 25°C
2
1.0E+00
= 20 V
0.0854 F
0.0710 W
V
I
D
DS
V
Figure 8. Gate Charge versus
= 1.2 A
DS
Normalized to qja at 10s.
= 25 V
4
Gate−To−Source Voltage
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Q
R
THERMAL LIMIT
PACKAGE LIMIT
g
Safe Operating Area
DS(on)
, TOTAL GATE CHARGE (nC)
0.2706 W
0.3074 F
Mounted on 2″ sq. FR4 board (1″ sq. 2 oz. Cu 0.06″
thick single sided) with one die operating, 10s max.
1
6
1.0E+01
LIMIT
dc
1.7891 F
8
0.5776 W
10 ms
10
1.0E+02
10
0.7086 W
107.55 F
100 ms
12
10 ms
Ambient
14
1.0E+03
16
100