P0061 Terasic Technologies Inc, P0061 Datasheet
P0061
Specifications of P0061
Related parts for P0061
P0061 Summary of contents
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Chapter 1 DE2‐115 Package ............................................................................... 4 1.1 Package Contents .......................................................................................................................................4 1.2 The DE2-115 Board Assembly ...................................................................................................................5 1.3 Getting Help ...............................................................................................................................................6 Chapter 2 Introduction of the Altera DE2‐115 Board .......................................... 7 2.1 Layout and Components.............................................................................................................................7 2.2 Block Diagram of the DE2-115 Board .......................................................................................................9 2.3 Power-up the DE2-115 Board ..................................................................................................................12 ...
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Using LEDs ..............................................................................................................................................34 4.4 Using the 7-segment Displays ..................................................................................................................36 4.5 Clock Circuitry .........................................................................................................................................38 4.6 Using the LCD Module ............................................................................................................................39 4.7 High Speed Mezzanine Card ....................................................................................................................40 4.8 Using the Expansion Header ....................................................................................................................45 4.9 Using 14-pin General Purpose I/O Connector..........................................................................................50 4.10 ...
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IR Receiver Demonstration ......................................................................................................................96 6.10 Music Synthesizer Demonstration........................................................................................................100 6.11 Audio Recording and Playing...............................................................................................................103 6.12 Web Server Demonstration...................................................................................................................106 Chapter 7 Appendix ....................................................................................... 115 7.1 Revision History..................................................................................................................................... 115 7.2 Copyright Statement ............................................................................................................................... 115 3 ...
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The DE2-115 package contains all components needed to use the DE2-115 board in conjunction with a computer that runs the Microsoft Windows OS ...
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Bag of six rubber (silicon) covers for the DE2-115 board stands. The bag also contains some extender pins, which can be used to facilitate easier probing with testing equipment of the board’s I/O expansion headers. • Clear plastic cover ...
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Here are the addresses where you can get help if you encounter ...
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Introduction of the Altera DE2-115 Board This chapter presents the features and design characteristics of the DE2-115 board ...
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The DE2-115 board has many features that allow users to implement a wide range of designed circuits, from simple circuits to various multimedia projects. The following hardware is provided on the DE2-115 board: • Altera Cyclone® IV 4CE115 FPGA device ...
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One 40-pin Expansion Header with diode protection • One High Speed Mezzanine Card (HSMC) connector • 16x2 LCD module In addition to these hardware features, the DE2-115 board has software support for standard I/O interfaces and a control panel ...
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Following is more detailed information about the blocks • Cyclone IV EP4CE115F29 device • 114,480 LEs • 432 M9K ...
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Configurable I/O standards (voltage levels:3.3/2.5/1.8/1.5V) • VGA-out connector o VGA DAC (high speed triple DACs) • DB9 serial connector for RS-232 port with flow control • PS/2 mouse/keyboard ...
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• Desktop DC input • Switching and step-down regulators LM3150MH ...
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You can also connect a microphone to the microphone-in connector on the DE2-115 board; your voice will be mixed with the music playing on the audio player Figure 2-4 The default VGA output pattern 13 ...
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The DE2-115 board comes with a Control Panel facility that allows users to access various components on the board from a host computer. The host computer communicates with the board through a USB connection. The facility can be used to ...
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The DE2_115_ControlPanel.sof bit stream is loaded automatically as soon as the DE2_115_control_panel.exe is launched case the connection is disconnected, click on CONNECT where the .sof will be re-loaded onto the board. 7. Note, the Control Panel will ...
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Figure 3-2 The DE2-115 Control Panel concept The DE2-115 Control Panel can be used to light up LEDs, change the values displayed on 7-segment and LCD displays, monitor buttons/switches status, read/write the SDRAM, SRAM, EEPROM and Flash Memory, monitor the ...
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Choosing the 7-SEG tab leads to the window shown in the left-right arrows to control the 7-SEG patterns on the DE2-115 board which are updated immediately. Note that the dots of the 7-SEGs are not enabled on DE2-115 board. Figure ...
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Choosing the LCD tab leads to the window in by typing it in the LCD box then pressing the Set button. The ability to set arbitrary values into simple display devices is not needed in typical design activities. However, it ...
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Figure 3-6 Monitoring switches and buttons The ability to check the status of push-button and slide switch is not needed in typical design activities. However, it provides users a simple mechanism for verifying if the buttons and switches are functioning ...
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A 16-bit word can be written into the SDRAM by entering the address of the desired location, specifying the data to be written, and pressing the Write button. Contents of the location can be read by pressing the Read button. ...
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The Sequential Read function is used to read the contents of the SDRAM and fill them into a file as follows: 1. Specify the starting address in the Address box. 2. Specify the number of bytes to be copied into ...
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The Control Panel provides users a PS/2 monitoring tool which monitors the real-time status ...
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The function is designed to read the identification and specification information of the SD Card. The 4-bit SD MODE is used to ...
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Choosing the RS-232 tab leads to the window in 2. Plug in a RS-232 9-pin male to female cable from PC to RS-232 port or a RS-232 loopback cable directly to RS-232 port. 3. The RS-232 settings are provided ...
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Choosing the VGA tab leads to the window in 2. Plug a D-sub cable to VGA connector of the DE2-115 board and LCD/CRT monitor. 3. The LCD/CRT monitor will display the same color pattern on the control panel window. ...
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Figure 3-13 HSMC loopback verification test performed under Control Panel From the ...
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Figure 3-14 Testing the IR receiver using remote controller The ...
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Figure 3-15 The block diagram of the DE2-115 control panel 28 ...
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This chapter gives instructions for using the DE2-115 board and describes each of its peripherals ...
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HSMC connector that will form a close JTAG loop chain on DE2-115 board (See only the on board FPGA device (Cyclone IV E) will be detected by Quartus II programmer. If users want to include another FPGA device or interface ...
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Configuring the FPGA in JTAG Mode Figure 4-3 illustrates the JTAG configuration setup. To download a configuration bit stream into the Cyclone IV E FPGA, perform the following steps: • Ensure that power is applied to the DE2-115 board • ...
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Configuring the EPCS64 in AS Mode Figure 4-5 illustrates the AS configuration setup. To download a configuration bit stream into the EPCS64 serial configuration device, perform the following steps: • Ensure that power is applied to the DE2-115 board. • ...
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Figure 4-6 Connections between the push-button and Cyclone IV E FPGA Pushbutton depressed Before Debouncing Schmitt Trigger Debounced There are also 18 slide switches on the DE2-115 board (See debounced, and are assumed for use as level-sensitive data inputs to ...
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Figure 4-8 Connections between the slide switches and Cyclone IV E FPGA There are 27 user-controllable ...
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Table 4-1 Pin Assignments for Slide Switches Signal Name FPGA Pin No. SW[0] PIN_AB28 SW[1] PIN_AC28 SW[2] PIN_AC27 SW[3] PIN_AD27 SW[4] PIN_AB27 SW[5] PIN_AC26 SW[6] PIN_AD26 SW[7] PIN_AB26 SW[8] PIN_AC25 SW[9] PIN_AB25 SW[10] PIN_AC24 SW[11] PIN_AB24 SW[12] PIN_AB23 SW[13] PIN_AA24 ...
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LEDR[15] PIN_G15 LEDR[16] PIN_G16 LEDR[17] PIN_H15 LEDG[0] PIN_E21 LEDG[1] PIN_E22 LEDG[2] PIN_E25 LEDG[3] PIN_E24 LEDG[4] PIN_H21 LEDG[5] PIN_G20 LEDG[6] PIN_G22 LEDG[7] PIN_G21 LEDG[8] PIN_F17 ...
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HEX0[5] PIN_J22 HEX0[6] PIN_H22 HEX1[0] PIN_M24 HEX1[1] PIN_Y22 HEX1[2] PIN_W21 HEX1[3] PIN_W22 HEX1[4] PIN_W25 HEX1[5] PIN_U23 HEX1[6] PIN_U24 HEX2[0] PIN_AA25 HEX2[1] PIN_AA26 HEX2[2] PIN_Y25 HEX2[3] PIN_W26 HEX2[4] PIN_Y26 HEX2[5] PIN_W27 HEX2[6] PIN_W28 HEX3[0] PIN_V21 HEX3[1] PIN_U21 HEX3[2] PIN_AB20 HEX3[3] PIN_AA21 ...
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HEX7[2] PIN_AG17 HEX7[3] PIN_AH17 HEX7[4] PIN_AF17 HEX7[5] PIN_AG18 HEX7[6] PIN_AA14 ...
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The LCD module has built-in fonts and can be used to display text by ...
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LCD_DATA[2] PIN_L2 LCD_DATA[1] PIN_L1 LCD_DATA[0] PIN_L3 LCD_EN PIN_L4 LCD_RW PIN_M1 LCD_RS PIN_M2 LCD_ON PIN_L5 LCD_BLON PIN_L6 ...
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Figure 4-13 HSMC VCCIO supply voltage setting header Table 4-8 Jumper Settings for different I/O Standards JP7 Jumper Settings Supplied Voltage to VCCIO5 & VCCIO6 IO Voltage of HSMC Connector (JP8) Short Pins 1 and 2 1.5V Short Pins 3 ...
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Figure 4-14 LVDS interface on HSMC connector and Cyclone IV E FPGA Table 4-9 Pin Assignments for HSMC connector FPGA Pin Signal Name No. HSMC_CLKIN0 PIN_AH15 HSMC_CLKIN_N1 PIN_J28 HSMC_CLKIN_N2 PIN_Y28 HSMC_CLKIN_P1 PIN_J27 HSMC_CLKIN_P2 PIN_Y27 HSMC_CLKOUT0 PIN_AD28 HSMC_CLKOUT_N1 PIN_G24 HSMC_CLKOUT_N2 PIN_V24 ...
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HSMC_RX_D_N[1] PIN_C27 HSMC_RX_D_N[2] PIN_E26 HSMC_RX_D_N[3] PIN_G26 HSMC_RX_D_N[4] PIN_H26 HSMC_RX_D_N[5] PIN_K26 HSMC_RX_D_N[6] PIN_L24 HSMC_RX_D_N[7] PIN_M26 HSMC_RX_D_N[8] PIN_R26 HSMC_RX_D_N[9] PIN_T26 HSMC_RX_D_N[10] PIN_U26 HSMC_RX_D_N[11] PIN_L22 HSMC_RX_D_N[12] PIN_N26 HSMC_RX_D_N[13] PIN_P26 HSMC_RX_D_N[14] PIN_R21 HSMC_RX_D_N[15] PIN_R23 HSMC_RX_D_N[16] PIN_T22 HSMC_RX_D_P[0] PIN_F24 HSMC_RX_D_P[1] PIN_D26 HSMC_RX_D_P[2] PIN_F26 HSMC_RX_D_P[3] PIN_G25 ...
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HSMC_RX_D_P[7] PIN_M25 HSMC_RX_D_P[8] PIN_R25 HSMC_RX_D_P[9] PIN_T25 HSMC_RX_D_P[10] PIN_U25 HSMC_RX_D_P[11] PIN_L21 HSMC_RX_D_P[12] PIN_N25 HSMC_RX_D_P[13] PIN_P25 HSMC_RX_D_P[14] PIN_P21 HSMC_RX_D_P[15] PIN_R22 HSMC_RX_D_P[16] PIN_T21 HSMC_TX_D_N[0] PIN_D28 HSMC_TX_D_N[1] PIN_E28 HSMC_TX_D_N[2] PIN_F28 HSMC_TX_D_N[3] PIN_G28 HSMC_TX_D_N[4] PIN_K28 HSMC_TX_D_N[5] PIN_M28 HSMC_TX_D_N[6] PIN_K22 HSMC_TX_D_N[7] PIN_H24 HSMC_TX_D_N[8] PIN_J24 HSMC_TX_D_N[9] PIN_P28 ...
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HSMC_TX_D_N[14] PIN_U28 HSMC_TX_D_N[15] PIN_V28 HSMC_TX_D_N[16] PIN_V22 HSMC_TX_D_P[0] PIN_D27 HSMC_TX_D_P[1] PIN_E27 HSMC_TX_D_P[2] PIN_F27 HSMC_TX_D_P[3] PIN_G27 HSMC_TX_D_P[4] PIN_K27 HSMC_TX_D_P[5] PIN_M27 HSMC_TX_D_P[6] PIN_K21 HSMC_TX_D_P[7] PIN_H23 HSMC_TX_D_P[8] PIN_J23 HSMC_TX_D_P[9] PIN_P27 HSMC_TX_D_P[10] PIN_J25 HSMC_TX_D_P[11] PIN_L27 HSMC_TX_D_P[12] PIN_V25 HSMC_TX_D_P[13] PIN_R27 HSMC_TX_D_P[14] PIN_U27 HSMC_TX_D_P[15] PIN_V27 HSMC_TX_D_P[16] PIN_U22 ...
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GND pins. Figure 4-15 shows the I/O distribution of the GPIO connector. The maximum power consumption of the daughter card that connects to GPIO port is shown in Table 4-10 Power Supply of the Expansion Header Supplied Voltage 5V 3.3V ...
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The voltage level of the I/O pins on the expansion headers can be adjusted to 3.3V, 2.5V, 1.8V, or 1.5V using JP6 (The default value is 3.3V, see connected to Bank 4 of the FPGA and the VCCIO voltage (VCCIO4) ...
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Note : Users who want to use daughter card on GPIO connector need to pay close attention to the I/O standard between DE2-115 GPIO connector pins and daughter card system. For example, if the I/O standard of GPIO pins on ...
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Table 4-12 Pin Assignments for Expansion Headers Signal Name FPGA Pin No. GPIO[0] PIN_AB22 GPIO[1] PIN_AC15 GPIO[2] PIN_AB21 GPIO[3] PIN_Y17 GPIO[4] PIN_AC21 GPIO[5] PIN_Y16 GPIO[6] PIN_AD21 GPIO[7] PIN_AE16 GPIO[8] PIN_AD15 GPIO[9] PIN_AE15 GPIO[10] PIN_AC19 GPIO[11] PIN_AF16 GPIO[12] PIN_AD19 GPIO[13] PIN_AF15 ...
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GPIO[29] PIN_AF26 GPIO[30] PIN_AE20 GPIO[31] PIN_AG23 GPIO[32] PIN_AF20 GPIO[33] PIN_AH26 GPIO[34] PIN_AH23 GPIO[35] PIN_AG26 ...
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The DE2-115 board includes a 15-pin D-SUB connector for VGA output. The VGA synchronization signals are ...
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Note: The RGB data bus on DE2-115 board is 8 bit instead of 10 bit on DE2/DE2-70 board. Figure 4-22 VGA horizontal timing specification Table 4-14 VGA Horizontal Timing Specification VGA mode Configuration Resolution(HxV) VGA(60Hz) 640x480 VGA(85Hz) 640x480 SVGA(60Hz) 800x600 ...
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Signal Name FPGA Pin No. VGA_R[0] PIN_E12 VGA_R[1] PIN_E11 VGA_R[2] PIN_D10 VGA_R[3] PIN_F12 VGA_R[4] PIN_G10 VGA_R[5] PIN_J12 VGA_R[6] PIN_H8 VGA_R[7] PIN_H10 VGA_G[0] PIN_G8 VGA_G[1] PIN_G11 VGA_G[2] PIN_F8 VGA_G[3] PIN_H12 VGA_G[4] PIN_C8 VGA_G[5] PIN_B8 VGA_G[6] PIN_F10 VGA_G[7] PIN_C9 VGA_B[0] PIN_B10 VGA_B[1] ...
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Figure 4-23 Connections between FPGA and Audio CODEC Table 4-17 Audio CODEC Pin Assignments Signal Name FPGA Pin No. AUD_ADCLRCK PIN_C2 AUD_ADCDAT PIN_D2 AUD_DACLRCK PIN_E3 AUD_DACDAT PIN_D1 AUD_XCK PIN_E1 AUD_BCLK PIN_F2 I2C_SCLK PIN_B7 I2C_SDAT PIN_A8 Note: If the HSMC loopback ...
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Figure 4-24 Connections between FPGA and ZT3232 (RS-232) chip Signal Name FPGA Pin No. UART_RXD PIN_G12 UART_TXD PIN_G9 UART_CTS PIN_G14 UART_RTS PIN_J13 ...
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Figure 4-26 Y-Cable use for both Keyboard and Mouse Signal Name FPGA Pin No. PS2_CLK PIN_G6 PS2_DAT PIN_H5 PS2_CLK2 PIN_G5 PS2_DAT2 PIN_F5 ...
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You will need to perform a hardware reset after any change for enabling new settings. and Table 4-22 describe the working mode settings for ENET0 PHY (U8) and ENET1 PHY (U9) respectively. In addition dynamically configurable to support ...
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Table 4-22 Jumper Settings for Working Mode of ENET1 (U9) JP2 Jumper Settings Short Pins 1 and 2 Short Pins 2 and 3 Table 4-23 Pin Assignments for Fast Ethernet Signal Name FPGA Pin No. ENET0_GTX_CLK PIN_A17 ENET0_INT_N PIN_A21 ENET0_LINK100 ...
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ENET1_TX_CLK PIN_C22 ENET1_TX_DATA[0] PIN_C25 ENET1_TX_DATA[1] PIN_A26 ENET1_TX_DATA[2] PIN_B26 ENET1_TX_DATA[3] PIN_C26 ENET1_TX_EN PIN_B25 ENET1_TX_ER PIN_A25 ENETCLK_25 PIN_A14 ...
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Note: If the HSMC loopback adapter is mounted, the I2C_SCL will be directly routed back to I2C_SDA. Because audio chip, TV decoder chip and HSMC share one I2C bus, therefore audio and video chip won’t function correctly. Table 4-24 TV ...
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The DE2-115 board provides both USB host and device interfaces using the Philips ISP1362 ...
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OTG_DATA[8] PIN_H3 OTG_DATA[9] PIN_H4 OTG_DATA[10] PIN_G1 OTG_DATA[11] PIN_G2 OTG_DATA[12] PIN_G3 OTG_DATA[13] PIN_F1 OTG_DATA[14] PIN_F3 OTG_DATA[15] PIN_G4 OTG_CS_N PIN_A3 OTG_RD_N PIN_B3 OTG_WR_N PIN_A4 OTG_RST_N PIN_C5 OTG_INT[0] PIN_A6 OTG_INT[1] PIN_D5 OTG_DACK_N[0] PIN_C4 OTG_DACK_N[1] PIN_D4 OTG_DREQ[0] PIN_J1 OTG_DREQ[1] PIN_B4 OTG_FSPEED PIN_C6 OTG_LSPEED PIN_B6 ...
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Signal Name FPGA Pin No. IRDA_RXD PIN_Y15 SRAM The DE2-115 board has 2MB SRAM ...
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Figure 4-34 Connections between FPGA and SDRAM FLASH The board is assembled with 8MB of flash memory using an 8-bit data bus. The device uses 3.3V CMOS signaling standard. Because of its non-volatile property usually used for storing ...
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EEPROM The board has 32Kb EEPROM. With the benefit of I2C bus, users could use it as residence of user data like version information, MAC address or other description substance. schematic view of the EEPROM. The configured access address of ...
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Figure 4-37 Connections between FPGA and SD Card Socket Signal Name FPGA Pin No. SRAM_ADDR[0] PIN_AB7 SRAM_ADDR[1] PIN_AD7 SRAM_ADDR[2] PIN_AE7 SRAM_ADDR[3] PIN_AC7 SRAM_ADDR[4] PIN_AB6 SRAM_ADDR[5] PIN_AE6 SRAM_ADDR[6] PIN_AB5 SRAM_ADDR[7] PIN_AC5 SRAM_ADDR[8] PIN_AF5 SRAM_ADDR[9] PIN_T7 SRAM_ADDR[10] PIN_AF2 SRAM_ADDR[11] PIN_AD3 SRAM_ADDR[12] PIN_AB4 ...
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SRAM_DQ[7] PIN_AF7 SRAM_DQ[8] PIN_AD1 SRAM_DQ[9] PIN_AD2 SRAM_DQ[10] PIN_AE2 SRAM_DQ[11] PIN_AE1 SRAM_DQ[12] PIN_AE3 SRAM_DQ[13] PIN_AE4 SRAM_DQ[14] PIN_AF3 SRAM_DQ[15] PIN_AG3 SRAM_OE_N PIN_AD5 SRAM_WE_N PIN_AE8 SRAM_CE_N PIN_AF8 SRAM_LB_N PIN_AD4 SRAM_UB_N PIN_AC4 Signal Name FPGA Pin No. DRAM_ADDR[0] PIN_R6 DRAM_ADDR[1] PIN_V8 DRAM_ADDR[2] PIN_U8 DRAM_ADDR[3] ...
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DRAM_DQ[16] PIN_M8 DRAM_DQ[17] PIN_L8 DRAM_DQ[18] PIN_P2 DRAM_DQ[19] PIN_N3 DRAM_DQ[20] PIN_N4 DRAM_DQ[21] PIN_M4 DRAM_DQ[22] PIN_M7 DRAM_DQ[23] PIN_L7 DRAM_DQ[24] PIN_U5 DRAM_DQ[25] PIN_R7 DRAM_DQ[26] PIN_R1 DRAM_DQ[27] PIN_R2 DRAM_DQ[28] PIN_R3 DRAM_DQ[29] PIN_T3 DRAM_DQ[30] PIN_U4 DRAM_DQ[31] PIN_U1 DRAM_BA[0] PIN_U7 DRAM_BA[1] PIN_R4 DRAM_DQM[0] PIN_U2 DRAM_DQM[1] PIN_W4 ...
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FL_ADDR[15] PIN_Y10 FL_ADDR[16] PIN_AA8 FL_ADDR[17] PIN_AH12 FL_ADDR[18] PIN_AC12 FL_ADDR[19] PIN_AD12 FL_ADDR[20] PIN_AE10 FL_ADDR[21] PIN_AD10 FL_ADDR[22] PIN_AD11 FL_DQ[0] PIN_AH8 FL_DQ[1] PIN_AF10 FL_DQ[2] PIN_AG10 FL_DQ[3] PIN_AH10 FL_DQ[4] PIN_AF11 FL_DQ[5] PIN_AG11 FL_DQ[6] PIN_AH11 FL_DQ[7] PIN_AF12 FL_CE_N PIN_AG7 FL_OE_N PIN_AG8 FL_RST_N PIN_AE11 FL_RY PIN_Y1 ...
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This chapter describes how users can create a custom design project on the DE2-115 board by using DE2-115 Software Tool – DE2-115 System Builder ...
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The top-level design file contains top-level verilog HDL wrapper for users to add their own design/logic. The Quartus II setting file contains information such as FPGA device type, top-level pin assignment, and I/O standard for each user-defined I/O pin. Finally, ...
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Figure 5-2 The DE2-115 System Builder window Input Project Name Input project name as show in Project Name: Type in an appropriate name here, it will automatically be assigned as the name of your top-level design entity. Figure 5-3 The ...
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System Configuration Under System Configuration users are given the flexibility of enabling their choice of included components on the DE2-115 as shown in where users can enable or disable a component according to their design by simply marking a check ...
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The “Prefix Name” optional feature which denotes the prefix pin name of the daughter card assigned in your design. Users may leave this field empty. HSMC Expansion Users can connect HSMC-interfaced daughter cards onto HSMC located on the ...
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The “Prefix Name” optional feature that denotes the pin name of the daughter card assigned in your design. Users may leave this field empty. Project Setting Management The DE2-115 System Builder also provides functions to restore default setting, ...
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Project Generation When users press the Generate button, the DE2-115 System Builder will generate the corresponding Quartus II files and documents as listed in the Table 5-1 The files generated by DE2-115 System Builder No. Filename 1 <Project name>.v 2 ...
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Examples of Advanced Demonstrations This chapter provides a number of examples of advanced circuits implemented on the DE2-115 board. These circuits provide demonstrations of the major features on the board, such as its audio and video capabilities, USB, and Ethernet ...
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EPCS64 device), download the bit stream to the board by using either JTAG or AS programming • You should now be able to observe that the 7-segment displays are displaying a sequence of characters, and the red and ...
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Finally, the YcrCb_to_RGB block converts the YcrCb data into RGB data output. The VGA Controller block generates standard VGA synchronous signals VGA_HS and VGA_VS to enable the display on a VGA monitor. Figure 6-1 Block diagram of the TV box ...
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Note: If the HSMC loopback adapter is mounted, the I2C_SCL will be directly routed back to I2C_SDA. Because audio chip, TV decoder chip and HSMC share one I2C bus, therefore audio and video chip won’t function correctly. Figure 6-2 illustrates ...
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DE2-115 board. When the mouse moves, the Nios II processor is able to keep track of the movement and record frame buffer memory. The VGA Controller will overlap the data stored in the frame ...
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Figure 6-4 illustrates the setup for this demonstration. Figure 6-4 The setup for the USB paintbrush demonstration ...
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USB packet to the board, which causes the Nios II processor to clear the hardware counter to zero. Figure 6-5 Block diagram of the USB device demonstration Demonstration Setup, File Locations, and Instructions • Project directory: DE2_115_NIOS_DEVICE_LED ...
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Note: execute DE2_115_NIOS_DEVICE_LED\demo_batch\nios_device_led.bat download .sof and .elf files. Figure 6-6 illustrates the setup for this demonstration. Figure 6-6 Setup for the USB device demonstration ...
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Figure 6-7 Block diagram of the Karaoke Machine demonstration Demonstration Setup, File Locations, and Instructions • Project directory: DE2_115_i2sound • Bit stream used: DE2_115_i2sound.sof or DE2_115_i2sound.pof • Connect a microphone to the microphone-in port (pink color) on the DE2-115 board ...
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Figure 6-8 The setup for the Karaoke Machine Many applications use a large external storage device, ...
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Figure 6-9 Block Diagram of the SD Card Demonstration Figure 6-10 shows the software stack of this demonstration. The Nios PIO block provides basic IO functions to access hardware directly. The functions are provided from Nios II system and the ...
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Figure 6-10 Software Stack of the SD Card Demonstration ...
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Figure 6-11 Insert SD Card for the SD Card Demonstration Figure 6-12 Running results of the SD Card demonstration ...
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Figure 6-13 shows the hardware block diagram of this demonstration. The system requires a 50 MHz clock provided from the board. The PLL generates a 100MHz clock for Nios II processor and the other controllers except for the audio controller. ...
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System Call Figure 6-14 Software Stack of the SD music player demonstration The audio chip should be configured before sending audio signal to the audio chip. The main program uses I2C protocol to configure the audio chip working in master ...
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Connect a headset or speaker to the DE2-115 board and you should be able to hear the music played from the SD Card • Press KEY3 on the DE2-115 board to play the next music file stored in the ...
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Figure 6-15 The setup for the SD music player demonstration offer this simple ...
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Data transmit from the device to controller After sending an enabling instruction to the PS/2 mouse at stream mode, the device starts to send displacement data out, which consists of 33 bits. The frame data is cut into three similar ...
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Figure 6-16 Waveforms on two lines while communication taking place Demonstration Setup, File Locations, and Instructions • Project directory: DE2_115_PS2_DEMO • Bit stream used : DE2_115_PS2_DEMO.sof • Load the bit stream into FPGA by executing DE2_115_PS2_DEMO\demo_batch\DE2_115_PS2_DEMO.bat • Plug in the ...
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HEX0 Low byte of X displacement HEX1 High byte of X displacement HEX2 Low byte of Y displacement HEX3 High byte of Y displacement Figure 6-17 illustrates the setup of this demonstration. Figure 6-17 The setup of the PS/2 Mouse ...
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Figure 6-18 Remote controller Table 6-3 Key code information for each Key on remote controller Key Key Code Key Key Code 0x0F 0x13 0x01 0x02 0x04 0x05 0x07 0x08 0x11 0x00 0x16 0x14 Lead Code 1bit Custom Code 16bits Key ...
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After the IR receiver on DE2-115 board receives this frame, it will directly transmit that to FPGA. In this demo, the receiver controller is implemented in the FPGA. As includes Code Detector, State Machine, and Shift Register. ...
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We can apply the IR receiver to many applications, such as integrating to the SD Card Demo, and you can also develop other related interesting applications with it. Demonstration Setup, File Locations, and Instructions • Project directory: DE2_115_IR • Bit ...
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This demonstration shows how to implement a Multi-tone Electronic Keyboard using DE2-115 ...
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Figure 6-23 Block diagram of the Music Synthesizer design Demonstration Setup, File Locations, and Instructions • Project directory: DE2_115_Synthesizer • Bit stream used: DE2_115_Synthesizer.sof or DE2-115_Synthesizer.pof • Connect a PS/2 Keyboard to the DE2-115 board. • Connect the VGA output ...
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Table 6-5 and Table 6-6 illustrate the usage of the slide switches, push-button switches (KEYs), PS/2 Keyboard. • Slide Switches and Push-buttons switches Table 6-5 Usage of the slide switches and push-buttons switches (KEYs) Signal Name Description KEY[0] Reset Circuit ...
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Figure 6-24 The Setup of the Music Synthesizer Demonstration This demonstration shows how ...
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Figure 6-25 Man-Machine Interface of Audio Recorder and Player Figure 6-26 shows the block diagram of the Audio Recorder and Player design. There are hardware and software parts in the block diagram. The software part stores the Nios II program ...
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Demonstration Setup, File Locations, and Instructions • Hardware Project directory: DE2_115_AUDIO • Bit stream used: DE2_115_AUDIO.sof • Software Project directory: DE2_115_AUDIO\software\ • Connect an Audio Source to the LINE-IN port of the DE2-115 board. • Connect a Microphone to MIC-IN ...
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This design example shows a HTTP server using the sockets interface of the NicheStack™ ...
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Figure 6-27 MII interface MAC Configuration 107 ...
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Figure 6-28 RGMII interface MAC Configuration In the MAC Options tab (See 88E1111. The MDIO Module should be included used to generate a 2.5MHz MDC clock for the PHY chip from the controller's source clock(here a 100MHz ...
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Once the Triple-Speed Ethernet IP configuration has been set and necessary hardware connections have been made as shown in Figure 6-29 MAC Options Configuration Figure 6-30, click on generate. 109 ...
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Figure 6-31 shows the connections for programmable 10/100Mbps Ethernet operation via MII. Figure 6-31 PHY connected to the MAC via MII Figure 6-32 shows the connections for programmable 10/100/1000Mbps Ethernet operation via RGMII. Figure 6-30 SOPC Builder 110 ...
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Figure 6-32 PHY connected to the MAC via RGMII After the SOPC hardware project has been built, develop the SOPC software project, whose basic architecture is shown in Figure necessary hardware to be implemented into the DE2-115 host board. The ...
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Figure 6-33 Nios II Program Software Architecture Finally, the detail descriptions for Software flow chart of the Web Server program are listed in below: Firstly, the Web Server program initiates the MAC and net device then calls the get_mac_addr() function ...
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Ethernet 1 respectively. Table 6-9 Ethernet Port and working mode. PHY project directory ENET0 Interface DE2_115_Web_Server\ RGMII interface DE2_115_WEB_SERVER_RGMII_ENET0 DE2_115_Web_Server\ MII interface DE2_115_WEB_SERVER_MII_ENET0 Demonstration Setup, File Locations, and Instructions The Following steps describe how to setup a Web Server demonstration ...
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Note: Or execute DE2_115_Web_Server\<Web Server Mode-Port Specific>\demo_batch\web_server.bat for downloading .sof and .elf files. Figure 6-34 System Principle Diagram Figure 6-35 Served web page for DE2-115 114 ...
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Version V1.0 V1.01 V1. ...