CS8420-CSR Cirrus Logic Inc, CS8420-CSR Datasheet - Page 32
CS8420-CSR
Manufacturer Part Number
CS8420-CSR
Description
Audio DSPs IC Digital Audio Sample Rate Convertr
Manufacturer
Cirrus Logic Inc
Datasheet
1.CS8420-CSZ.pdf
(94 pages)
Specifications of CS8420-CSR
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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10. CONTROL PORT REGISTER BIT DEFINITIONS
10.1
INCR
MAP6-MAP0
INCR
7
Memory Address Pointer (MAP)
Reserved registers must not be written to during normal operation. Some reserved registers are used for
test modes, which can completely alter the normal operation of the CS8420.
MAP6
This register defaults to 01
Auto-Increment Address Control Bit
0 -
1 -
Register address and function list
0 -
1 -
2 -
3 -
4 -
5 -
6 -
7 -
8 -
9 -
10 -
11 -
12 -
13 -
14 -
15 -
16 -
17 -
18 -
19 -
20 to 29 -
30 -
31 -
32 to 55 -
56 to 126 - Reserved
127 -
6
Auto-increment address off
Auto-increment address on
Reserved
Misc. Control 1
Misc. Control 2
Data Flow Control
Clock Source Control
Serial Audio Input Port Data Format
Serial Audio Output Port Data Format
Interrupt Register 1 Status
Interrupt Register 2 Status
Interrupt Register 1 Mask
Interrupt Register1 Mode (MSB)
Interrupt Register 1 Mode (LSB)
Interrupt Register 2 Mask
Interrupt Register 2 Mode (MSB)
Interrupt Register 2 Mode (LSB)
Receiver Channel Status Bits
Receiver Error Status
Receiver Error Mask
Channel Status Data Buffer Control
User Data Buffer Control
Q-channel Subcode Bytes 0 to 9
Sample Rate Ratio
Reserved
C-bit or U-bit Data Buffer
Chip ID and version register
MAP5
5
MAP4
4
MAP3
3
MAP2
2
MAP1
1
CS8420
DS245F4
MAP0
0
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