ISPPAC-CLK5510V-01T48C Lattice, ISPPAC-CLK5510V-01T48C Datasheet - Page 30

• Manufacturer Part Number: ISPPAC-CLK5510V-01T48C
• Description: Clock Drivers & Distribution PROGRAMMABLE CLOCK GENERATOR
• Manufacturer: Lattice

Specifications of ISPPAC-CLK5510V-01T48C

• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Maximum Operating Temperature: 70 C
• Package / Case: TQFP-100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
grammed by the user over a range of 0 to 15. The ispClock5500 family also supports both ‘fine’ and ‘coarse’ skew
modes. In fine skew mode, the unit skew ranges from 195ps to 390 ps, while in the coarse skew mode unit skew
varies from 390ps to 780ps. The value of one TU may be calculated from the VCO frequency (f
lowing expressions:
When an output driver is programmed to support a differential output mode, a single skew setting is applied to both
the BANKxA+ and BANKxB- signals. When the output driver is configured to support a single-ended output stan-
dard, each of the two single-ended outputs may be assigned independent skews.
By using the internal feedback path, and programming a skew into the feedback skew control, it is possible to
implement negative timing skews, in which the clock edge of interest appears at the ispClock5500’s output before
the corresponding edge is presented at the reference input. When the feedback skew unit is used in this way, the
resulting negative skew is added to whatever skew is specified for each output. For example, if the feedback skew
is set to 6TU, BANK1’s skew is 8TU and BANK2’s skew is 3TU, then BANK1’s effective output skew will be 2TU
(8TU-6TU), while BANK2’s effective skew will be -3TU (3TU-6TU). This negative skew will manifest itself as
BANK2’s outputs appearing to lead the input reference clock, appearing as a negative propagation delay.
Please note that the skew control units are only usable when the PLL is selected. In PLL bypass mode
(PLL_BYPASS=1), output skew settings will be ineffective and all outputs will exhibit skew consistent with the
device’s propagation delay and the individual delays inherent in the output drivers consistent with the logic stan-
dard selected.
Coarse Skew Mode
The ispClock5500 family provides the user with the option of obtaining longer skew delays at the cost of reduced
time resolution through the use of coarse skew mode. Coarse skew mode provides TU values ranging from 390ps
(f
coarse skew mode is selected, an additional divide-by-2 stage is effectively inserted between the VCO and the V-
divider bank, as shown in Figure 27. When assigning divider settings in coarse skew mode, one must account for
this additional divide-by-two so that the VCO still operates within its specified range (320-640MHz).
Figure 27. Additional Factor-of-2 Division in Coarse Mode
When one moves from fine skew mode to coarse skew mode with a given divider configuration, the VCO frequency
will attempt to double to compensate for the additional divide-by-2 stage. Because the f
however, one must modify the feedback path V-divider settings to bring f
(320MHz to 640MHz). This can be accomplished by dividing all V-divider settings by two. All output frequencies will
remain unchanged from what they were in fine mode. One drawback of moving from fine skew mode into coarse
skew mode is that it may not be possible to maintain consistent output frequencies, as only those V-divider settings
which are multiples of four (in fine mode) may be divided by two. For example, a V-divider setting of 24 will divide
down to 12, which is also a legal V-divider setting, whereas an initial setting of 26 would divide down to 13, which is
not a valid setting.
VCO
= 640MHz) to 780ps (f
For fine skew mode,
VCO
VCO
= 320MHz), which is twice as long as those provided in fine skew mode. When
TU
=
8f
÷2
1
vco
30
Mode
Coarse
Fine
Mode
For coarse skew mode,
VCO
V-dividers
ispClock5500 Family Data Sheet
back into its specified operating range
TU
=
4f
1
vco
VCO
Fout
range is not increased,
vco
) by using the fol-
(5)