LAN89218AQ SMSC, LAN89218AQ Datasheet - Page 102

• Manufacturer Part Number: LAN89218AQ
• Description: Ethernet ICs High Perform Chip 10/100 NonPCI Cntrl
• Manufacturer: SMSC

Specifications of LAN89218AQ

• Ethernet Connection Type: 10BASE-T, 100BASE-TX
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Product: Ethernet Controllers
• Standard Supported: IEEE802.3, IEEE802.3u
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Maximum Operating Temperature: + 85 C
• Package / Case: TQFP-100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Revision 1.3 (02-23-10)
5.3.17
5.3.18
BITS
BITS
31:0
31:0
Word Swap. This field only has significance if the device is operated in 16-
bit mode. In 32-bit mode, D[31:15] is always mapped to the high order word
and D[15:0] is always mapped to the low order word. In 16-bit mode, if this
field is set to 00000000h, or anything except 0xFFFFFFFFh, the LAN89218
maps words with address bit A[1]=1 to the high order words of the CSRs
and Data FIFOs, and words with address bit A[1]=0 to the low order words
of the CSRs and Data FIFOs. If this field is set to 0xFFFFFFFFh, the
LAN89218 maps words with address bit A[1]=1 to the low order words of
the CSRs and Data FIFOs, and words with address bit A[1]=0 to the high
order words of the CSRs and Data FIFOs.
Note: Please refer to
Note: Word swap is used in conjunction with the mixed endian functionality
Free Running SCLK Counter (FR_CNT):
This field reflects the value of a free-running 32-bit counter. At reset the
counter starts at zero and is incremented for every 25MHz cycle. When the
maximum count has been reached the counter will rollover. When read in
16-bit mode the count value is latched on the first read.
Note: The FREE_RUN counter can take up to 160 ns to clear after a reset
Note: This counter will run regardless of the power management states D0,
WORD_SWAP—Word Swap Control
This register controls how words from the host data bus are mapped to the CSRs and Data FIFOs
inside the LAN89218. The LAN89218 always sends data from the Transmit Data FIFO to the network
so that the low order word is sent first, and always receives data from the network to the Receive Data
FIFO so that the low order word is received first.
FREE_RUN—Free-Run 25MHz Counter
This register reflects the value of the free-running 25 MHz counter.
Offset:
Offset:
Operation"
to determine the final byte ordering. Refer to
Endian Support"
event.
D1 or D2.
for additional information.
Section 3.7.1, "32-bit vs. 16-bit Host Bus Width
for more information.
High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications
DESCRIPTION
DESCRIPTION
98h
9Ch
DATASHEET
102
Size:
Size:
Section 3.7.4, "Mixed
32 bits
32 bits
NASR
TYPE
TYPE
R/W
RO
SMSC LAN89218
00000000h
DEFAULT
DEFAULT
Datasheet
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