LAN89218AQ SMSC, LAN89218AQ Datasheet - Page 13

• Manufacturer Part Number: LAN89218AQ
• Description: Ethernet ICs High Perform Chip 10/100 NonPCI Cntrl
• Manufacturer: SMSC

Specifications of LAN89218AQ

• Ethernet Connection Type: 10BASE-T, 100BASE-TX
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Product: Ethernet Controllers
• Standard Supported: IEEE802.3, IEEE802.3u
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Maximum Operating Temperature: + 85 C
• Package / Case: TQFP-100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications
Datasheet
SMSC LAN89218
1.4
1.5
1.6
1.7
The transmit and receive data paths are separate within the MAC allowing for the highest performance
possible, especially in full duplex mode. The data paths connect to the PIO interface via separate
busses to increase performance. Payload data as well as transmit and receive status are passed on
these busses. A third internal bus is used to access the MAC’s Control and Status Registers (CSR’s).
This bus is accessible from the host through the PIO interface function.
On the backend, the MAC interfaces with the internal 10/100 PHY through a MII (Media Independent
Interface) port internal to the LAN89218. The MAC CSR's also provide a mechanism for accessing the
PHY’s internal registers through the internal SMI (Serial Management Interface) bus.
The MAC Interface Layer (MIL), within the MAC, contains a 2 kByte transmit and a 128 Byte receive
FIFO which is separate from the TX and RX FIFOs. The FIFOs within the MAC are not directly
accessible from the host interface. The differentiation between the TX/RX FIFO memory buffers and
the MAC buffers is that when the transmit or receive packets are in the MAC buffers, the host no longer
can control or access the TX or RX data. The MAC buffers (both TX and RX) are in effect the working
buffers of the Ethernet MAC logic. In the case of reception, the data must be moved first to the RX
FIFOs for the host to access the data. For TX operations, the MIL operates in store-and-forward mode
and will queue an entire frame before beginning transmission.
The Receive and Transmit FIFOs allow increased packet buffer storage to the MAC. The FIFOs are a
conduit between the host interface and the MAC through which all transmitted and received data and
status information is passed. Deep FIFOs allow a high degree of latency tolerance relative to the
various transport and OS software stacks thus reducing or minimizing overrun conditions. Like the
MAC, the FIFOs have separate receive and transmit data paths. In addition, the RX and TX FIFOs are
configurable in size, allowing increased flexibility.
The host bus interface provides a FIFO interface for the transmit and receive data paths, as well as
an interface for the LAN89218 Control and Status Registers (CSR’s).
The host bus interface is the primary bus for connection to the embedded host system. This interface
models an asynchronous SRAM. TX FIFO, RX FIFO, and CSR’s are accessed through this interface.
Programmed I/O transactions are supported.
The LAN89218 host bus interface supports 32-bit and 16-bit bus transfers. Internally, all data paths
are 32-bits wide. The LAN89218 can be interfaced to either Big-Endian or Little-Endian processors and
includes mixed endian support for FIFO accesses.
The LAN89218 supports a single programmable interrupt. The programmable nature of this interrupt
allows the user the ability to optimize performance dependent upon the application requirement. Both
the polarity and buffer type of the interrupt pin are configurable for the external interrupt processing.
The interrupt line can be configured as an open-drain output to facilitate the sharing of interrupts with
other devices. In addition, a programmable interrupt de-assertion interval is provided.
10/100 Ethernet MAC
Receive and Transmit FIFOs
Host Bus Interface (SRAM Interface)
Interrupt Controller
DATASHEET
13
Revision 1.3 (02-23-10)