DS21455 Maxim Integrated Products, DS21455 Datasheet - Page 143

• Manufacturer Part Number: DS21455
• Description: Network Controller & Processor ICs Quad E1-T1-J1 Single -Chip Transceiver (S
• Manufacturer: Maxim Integrated Products

Specifications of DS21455

• Product: Framer
• Number Of Transceivers: 4
• Data Rate: 64 Kbps
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Supply Current (max): 328 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Package / Case: BGA

24.2 HDLC Configuration
Basic configuration of the HDLC controllers is accomplished via the HxTC and HxRC registers.
Operating features such as CRC generation, zero stuffer, transmit and receive HDLC mapping options,
and idle flags are selected here. Also, the HDLC controllers are reset via these registers.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 0/Transmit CRC Defeat (TCRCD). A 2-byte CRC code is automatically appended to the outbound message. This bit can
be used to disable the CRC function.
Bit 1/Transmit Zero Stuffer Defeat (TZSD). The zero stuffer function automatically inserts a zero in the message field
(between the flags) after five consecutive ones to prevent the emulation of a flag or abort sequence by the data pattern. The
receiver automatically removes (de-stuffs) any zero after five ones in the message field.
Bit 2/Transmit End of Message (TEOM). Should be set to a one just before the last data byte of an HDLC packet is written
into the transmit FIFO at HxTF. If not disabled via TCRCD, the transmitter will automatically append a 2-byte CRC code to
the end of the message.
Bit 3/Transmit Flag/Idle Select (TFS). This bit selects the inter-message fill character after the closing and before the
opening flags (7Eh).
Bit 4/Transmit HDLC Mapping Select (THMS).
Bit 5/Transmit HDLC Reset (THR). Will reset the transmit HDLC controller and flush the transmit FIFO. An abort followed
by 7Eh or FFh flags/idle will be transmitted until a new packet is initiated by writing new data into the FIFO. Must be cleared
and set again for a subsequent reset.
Bit 6/Transmit End of Message and Loop (TEOML). To loop on a message, should be set to a one just before the last data
byte of an HDLC packet is written into the transmit FIFO. The message will repeat until the user clears this bit or a new
message is written to the transmit FIFO. If the host clears the bit, the looping message will complete then flags will be
transmitted until new message is written to the FIFO. If the host terminates the loop by writing a new message to the FIFO the
loop will terminate, one or two flags will be transmitted and the new message will start. If not disabled via TCRCD, the
transmitter will automatically append a 2-byte CRC code to the end of all messages. This is useful for transmitting consecutive
SS7 FISUs without host intervention.
Bit 7/Number Of Flags Select (NOFS).
0 = enable CRC generation (normal operation)
1 = disable CRC generation
0 = enable the zero stuffer (normal operation)
1 = disable the zero stuffer
0 = 7Eh
1 = FFh
0 = transmit HDLC assigned to channels
1 = transmit HDLC assigned to FDL (T1 mode), Sa Bits (E1 mode)
0 = normal operation
1 = reset transmit HDLC controller and flush the transmit FIFO
0 = send one flag between consecutive messages
1 = send two flags between consecutive messages
NOFS
7
0
TEOML
H1TC, H2TC
HDLC #1 Transmit Control, HDLC #2 Transmit Control
90h, A0h
6
0
THR
5
0
THMS
4
0
143 of 270
TFS
3
0
TEOM
2
0
TZSD
1
0
TCRCD
0
0