DS3112N+W Maxim Integrated Products, DS3112N+W Datasheet - Page 29

• Manufacturer Part Number: DS3112N+W
• Description: Network Controller & Processor ICs M13-E13-G.747 Mux an d T3-E3 Framer T3-E3
• Manufacturer: Maxim Integrated Products

Specifications of DS3112N+W

• Product: Framer
• Number Of Transceivers: 1
• Data Rate: 44.736 Mbps
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Supply Current (max): 150 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Package / Case: BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

2.9 JTAG Signal Description
Signal Name:
Signal Description:
Signal Type:
This signal is used to shift data into JTDI on the rising edge and out of JTDO on the falling edge. If not
used, this signal should be pulled high.
Signal Name:
Signal Description:
Signal Type:
Test instructions and data are clocked into this signal on the rising edge of JTCLK. If not used, this signal
should be pulled high. This signal has an internal pullup.
Signal Name:
Signal Description:
Signal Type:
Test instructions are clocked out of this signal on the falling edge of JTCLK. If not used, this signal
should be left open circuited.
Signal Name:
Signal Description:
Signal Type:
This signal is used to asynchronously reset the test access port controller. At power-up, JTRST must be
set low and then high. This action will set the device into the boundary scan bypass mode allowing
normal device operation. If boundary scan is not used, this signal should be held low. This signal has an
internal pullup.
Signal Name:
Signal Description:
Signal Type:
This signal is sampled on the rising edge of JTCLK and is used to place the test port into the various
defined IEEE 1149.1 states. If not used, this signal should be pulled high. This signal has an internal
pullup.
2.10 Supply, Test, Reset, and Mode Signal Description
Signal Name:
Signal Description:
Signal Type:
This active low asynchronous signal causes the device to be reset. When this signal is forced low, it
causes all of the internal registers to be forced to 00h and the high-speed T3/E3 ports as well as the low-
speed T1/E1 ports to source an unframed all ones data pattern. The device will be held in a reset state as
long as this signal is low. This signal should be activated after the hardware configuration signals (LIEN
and T3E3MS) and the clocks (FTCLK, LTCLK, HRCLK, and LITCLK) are stable and must be returned
high before the device can be configured for operation.
JTCLK
JTAG IEEE 1149.1 Test Serial Clock
Input
JTDI
JTAG IEEE 1149.1 Test Serial Data Input
Input (with internal 10kΩ pullup)
JTDO
JTAG IEEE 1149.1 Test Serial Data Output
Output
JTRST
JTAG IEEE 1149.1 Test Reset
Input (with internal 10kΩ pullup)
JTMS
JTAG IEEE 1149.1 Test Mode Select
Input (with internal 10kΩ pullup)
RST*
Global Hardware Reset
Input (with internal 10kΩ pullup)
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