DS3112N+W Maxim Integrated Products, DS3112N+W Datasheet - Page 31

• Manufacturer Part Number: DS3112N+W
• Description: Network Controller & Processor ICs M13-E13-G.747 Mux an d T3-E3 Framer T3-E3
• Manufacturer: Maxim Integrated Products

Specifications of DS3112N+W

• Product: Framer
• Number Of Transceivers: 1
• Data Rate: 44.736 Mbps
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Supply Current (max): 150 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Package / Case: BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

3 MEMORY MAP
Table 3-1. Memory Map
ADDRESS
0A
0C
2A
5A
5C
7A
7C
5E
6E
7E
00
02
04
06
08
10
12
14
16
18
20
22
24
26
28
30
32
34
36
40
42
44
46
50
52
54
56
58
60
62
70
72
74
76
78
80
ACRONYM
T1E1RAIS1
T1E1RAIS2
T1E1TAIS1
T1E1TAIS2
T1E1DLB1
T1E1DLB2
T3E3INFO
T1E1LLB1
T1E1LLB2
BERTBC0
BERTBC1
BERTRP0
BERTRP1
BERTEC0
BERTEC1
T1LBCR1
T1LBCR2
T2E2CR1
T2E2CR2
T1LBSR1
T1LBSR2
T1E1SDP
BERTMC
T2E2SR1
T2E2SR2
T3E3EIC
IT3E3SR
FEBECR
BERTC0
BERTC1
T1E1SIP
T3E3CR
T3E3SR
BPVCR
EXZCR
MRID
CPCR
FECR
IMSR
TEST
MC1
MC2
MC3
MSR
HCR
PCR
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Master Reset and ID Register
Master Configuration Register 1
Master Configuration Register 2
Master Configuration Register 3
Master Status Register
Interrupt Mask Register for MSR
Test Register
T3/E3 Control Register
T3/E3 Status Register
Interrupt Mask for T3E3SR
T3/E3 Information Register
T3/E3 Error Insert Control Register
T3/E3 Bipolar Violation (BPV) Count Register
T3/E3 Excessive Zero (EXZ) Count Register
T3/E3 Frame Error Count Register
T3 Parity Bit Error Count Register
T3 C-Bit Parity Error Count Register
T3 Far End Block Error or E3 RAI Count Register
T2/E2 Control Register 1
T2/E2 Control Register 2
T2/E2 Status Register 1
T2/E2 Status Register 2
T1/E1 Receive Path AIS Generation Control Register 1
T1/E1 Receive Path AIS Generation Control Register 2
T1/E1 Transmit Path AIS Generation Control Register 1
T1/E1 Transmit Path AIS Generation Control Register 2
T1/E1 Line Loopback Control Register 1
T1/E1 Line Loopback Control Register 2
T1/E1 Diagnostic Loopback Control Register 1
T1/E1 Diagnostic Loopback Control Register 2
T1 Line Loopback Command Register 1
T1 Line Loopback Command Register 2
T1 Line Loopback Status Register 1
T1 Line Loopback Status Register 2
T1/E1 Select Register for Receive Drop Ports A and B
T1/E1 Select Register for Transmit Drop Ports A and B
BERT Mux Control Register
BERT Control 0
BERT Control 1
BERT Repetitive Pattern Set 0 (lower word)
BERT Repetitive Pattern Set 1 (upper word)
BERT Bit Counter 0 (lower word)
BERT Bit Counter 1 (upper word)
BERT Error Counter 0 (lower word)
BERT Error Counter 1 (upper word)
HDLC Control Register
31 of 133
REGISTER NAME
SECTION
4.1
4.2
4.2
4.2
4.3
4.3
4.4
5.2
5.3
5.3
5.3
5.3
5.4
5.4
5.4
5.4
5.4
5.4
6.2
6.2
6.4
6.4
6.4
6.4
6.4
6.4
7.1
7.1
7.2
7.2
7.3
7.3
7.6
7.6
7.4
7.4
8.1
8.1
8.1
8.1
8.1
8.1
8.1
8.1
8.1
9.1
DS3112