CS8900A-CQZR Cirrus Logic Inc, CS8900A-CQZR Datasheet - Page 108

• Manufacturer Part Number: CS8900A-CQZR
• Description: Ethernet ICs IC 10Mbps Ethernet Controller 5V
• Manufacturer: Cirrus Logic Inc

Specifications of CS8900A-CQZR

• Ethernet Connection Type: 10Base- 2, 10Base- 5, 10Base- F, 10Base- T
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Product: Ethernet Controllers
• Standard Supported: IEEE 802.3
• Data Rate: 10 Mbps
• Maximum Operating Temperature: + 70 C
• Package / Case: LQFP-100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6.2 Boundary Scan
Boundary Scan test mode provides an easy
and efficient board-level test for verifying that
the CS8900A has been installed properly.
Boundary Scan will check to see if the orienta-
tion of the chip is correct, and if there are any
open or short circuits.
Boundary Scan is controlled by the TEST pin.
When TEST is high, the CS8900A is config-
ured for normal operation. When TEST is low,
the following occurs:
•
•
•
•
For Boundary Scan to be enabled, AEN must
be low before TEST is driven low.
A complete Boundary Scan test is made up of
two separate cycles. The first cycle, known as
the Output Cycle, tests all digital output pins
and all bi-directional pins. The second cycle,
known as the Input Cycle, tests all digital input
pins and all bi-directional pins.
6.2.1 Output Cycle
During the Output Cycle, the falling edge of
AEN causes each of the 17 digital output pins
and each of the 17 bi-directional pins to be
driven low, one at a time. The cycle begins
with LINKLED and advances in order counter-
108
the CS8900A enters Boundary Scan test
mode and stays in this mode as long as
TEST is low;
the CS8900A goes through an internal re-
set and remains in internal reset as long as
TEST is low;
the AEN pin, normally the ISA bus Address
Enable, is redefined to become the Bound-
ary Scan shift clock input; and
all digital outputs and bi-directional pins are
placed in a high-impedance state (this
electrically isolates the CS8900A digital
outputs from the rest of the circuit board).
CIRRUS LOGIC PRODUCT DATASHEET
clockwise around the chip through all 34 pins.
This test is referred to as a "walking 0" test.
The following is a list of output pins and bi-di-
rectional pins that are tested during the Output
Cycle:
The output pins not included in this test are:
6.2.2 Input Cycle
During the Input Cycle, the falling edge of AEN
causes the state of each selected pin to be
transferred to EEDataOut (that is, EEDataOut
will be high or low depending on the input level
of the selected pin). This cycle begins with
SLEEP and advances clockwise through each
of 33 input pins (all digital input pins except for
AEN) and each of the 17 bi-directional pins,
one pin at a time.
The following is a list of input pins and bi-direc-
tional pins that are tested during the Input Cy-
cle:
SD08-SD15 27-24, 21-18
EEDataOut
Pin Name
Pin Name
Pin Name
EEDataIn
CHIPSEL
DMACK2
DMARQ2
DMARQ1
DMARQ0
INTRQ2
CSOUT
ELCS
EECS
EESK
ELCS
TXD+
DO+
DO-
Crystal LAN™ Ethernet Controller
Pin #
Pin #
Pin #
12
2
6
7
13
15
17
30
83
84
87
11
2
3
4
5
Table 41.
Table 39.
Table 40.
SA12 - SA19 50-54, 58-60
SA0 - SA11
REFRESH
Pin Name
MEMCS16
SD0 - SD7 65-68, 71-74
IOCHRDY
Pin Name
Pin Name
BSTATUS
LINKLED
LANLED
INTRQ1
INTRQ0
INTRQ3
IOCS16
SBHE
XTAL2
TXD-
RES
CS8900A
37-48
Pin #
Pin #
Pin #
DS271F5
36
49
100
31
32
33
34
35
64
78
99
88
93
98