CS8900A-CQZR Cirrus Logic Inc, CS8900A-CQZR Datasheet - Page 99

• Manufacturer Part Number: CS8900A-CQZR
• Description: Ethernet ICs IC 10Mbps Ethernet Controller 5V
• Manufacturer: Cirrus Logic Inc

Specifications of CS8900A-CQZR

• Ethernet Connection Type: 10Base- 2, 10Base- 5, 10Base- F, 10Base- T
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Product: Ethernet Controllers
• Standard Supported: IEEE 802.3
• Data Rate: 10 Mbps
• Maximum Operating Temperature: + 70 C
• Package / Case: LQFP-100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DS271F5
5.5.6 Receive DMA Summary
Table 30 summarize the Receive DMA config-
uration options supported by the CS8900A.
5.6 Transmit Operation
5.6.1 Overview
Packet transmission occurs in two phases. In
the first phase, the host moves the Ethernet
frame into the CS8900A's buffer memory. The
first phase begins with the host issuing a
Transmit Command.
This informs the CS8900A that a frame is to be
transmitted and tells the chip when (i.e. after 5,
381, or 1021 bytes have been transferred or
after the full frame has been transferred to the
CS8900A) and how the frame should be sent
(i.e. with or without CRC, with or without pad
bits, etc.). The host follows the Transmit Com-
mand with the Transmit Length, indicating how
much buffer space is required. When buffer
space is available, the host writes the Ethernet
frame into the CS8900A's internal memory,
using either Memory or I/O space.
In the second phase of transmission, the
CS8900A converts the frame into an Ethernet
packet then transmits it onto the network. The
second phase begins with the CS8900A trans-
mitting the preamble and Start-of-Frame de-
limiter as soon as the proper number of bytes
has been transferred into its transmit buffer (5,
CS8900A
Crystal LAN™ Ethernet Controller
RxCFG,Bit 9)
RxDMAonly
(Register 3,
1
1
0
0
0
AutoRxDMAiE
RxCFG, Bit A)
(Register 3,
NA
NA
1
1
0
BufCFG, Bit 7)
Table 30. Receive DMA Configuration Options
(Register B,
RxDMAiE
CIRRUS LOGIC PRODUCT DATASHEET
NA
0
1
0
1
RxCFG, Bit 8)
(Register 3,
RxOKiE
NA
NA
NA
0
1
381, 1021 bytes or full frame, depending on
configuration). The preamble and Start-of-
Frame delimiter are followed by the data trans-
ferred into the on-chip buffer by the host (Des-
tination Address, Source Address, Length field
and LLC data). If the frame is less than 64
bytes, including CRC, the CS8900A adds pad
bits if configured to do so. Finally, the
CS8900A appends the proper 32-bit CRC val-
ue.
5.6.2 Transmit Configuration
After each reset, the CS8900A must be config-
ured for transmit operation. This can be done
automatically using an attached EEPROM, or
by writing configuration commands to the
CS8900A's internal registers (see Section 3.4
on page 21). The items that must be config-
ured include which physical interface to use
and which transmit events cause interrupts.
5.6.2.1 Configuring the Physical Interface
Configuring the physical interface consists of
determining which Ethernet interface should
be active (10BASE-T or AUI), and enabling the
transmit logic for serial transmission. Configur-
ing the Physical Interface is accomplished via
Receive DMA used for all receive frames, without
interrupts.
Receive DMA used for all receive frames, with
BufEvent interrupts.
Auto-Switch DMA used if necessary, without inter-
rupts.
Auto-Switch DMA used if necessary, with RxEvent
and BufEvent interrupts possible.
Memory or I/O Mode only.
CS8900A Configuration
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