CS8900A-CQZR Cirrus Logic Inc, CS8900A-CQZR Datasheet - Page 81

• Manufacturer Part Number: CS8900A-CQZR
• Description: Ethernet ICs IC 10Mbps Ethernet Controller 5V
• Manufacturer: Cirrus Logic Inc

Specifications of CS8900A-CQZR

• Ethernet Connection Type: 10Base- 2, 10Base- 5, 10Base- F, 10Base- T
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Product: Ethernet Controllers
• Standard Supported: IEEE 802.3
• Data Rate: 10 Mbps
• Maximum Operating Temperature: + 70 C
• Package / Case: LQFP-100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DS271F5
5.2.2.1 Configuring the Physical Interface
Configuring the physical interface consists of
determining which Ethernet interface should
be active, and enabling the receive logic for
serial reception. This is done via the LineCTL
register (Register 13) and is described in
Table19.
5.2.2.2 Choosing which Frame Types to Ac-
cept
The RxCTL register (Register 5) is used to de-
termine which frame types will be accepted by
the CS8900A (a receive frame is said to be
"accepted" when the frame is buffered, either
on chip or in host memory via DMA). Table 20
describes the configuration bits in this register.
Refer to Section 5.2.10 on page 87 for a de-
tailed description of Destination Address filter-
ing.
* Must also meet the criteria programmed into bits 8, C, D, and E.
CS8900A
Crystal LAN™ Ethernet Controller
Bit
Bit Bit Name
E LoRx Squelch When set, receiver squelch level
6
8
9 AutoAUI/10BT When set, automatic interface
6
7
8
9
MulticastA When set, Multicast frames that pass
IAHashA When set, Individual Address frames
cuousA
RxOKA
Promis
Table 19. Physical Interface Configuration
Bit Name
SerRxON
AUIonly
Table 20. Frame Acceptance Criteria
Register 13, LineCTL
that pass the hash filter are
accepted*.
When set, all frames are accepted*.
When set, frames with valid length
and CRC and that pass the DA filter
are accepted.
the hash filter are accepted*.
Register 5, RxCTL
When set, reception enabled.
When set, AUI selected (takes
precedence over AutoAUI/10BT).
selection enabled. When both bits
8 and 9 are clear, 10BASE-T
selected.
reduced by approximately 6 dB.
Operation
Operation
CIRRUS LOGIC PRODUCT DATASHEET
* Must also meet the criteria programmed into bits 8, C, D, and E.
5.2.2.3 Selecting which Events Cause Inter-
rupts
The RxCFG register (Register 3) and the Buf-
CFG register (Register B) are used to deter-
mine
interrupts to the host processor. Table 22 de-
scribes the interrupt enable (iE) bits in these
registers.
* Must also pass the DA filter before there is an interrupt.
5.2.2.4 Choosing How to Transfer Frames
The RxCFG register (Register 3) and the Bus-
CTL register (Register 17) are used to deter-
Bit Bit Name
Bit Bit Name
C CRCerrorA When set, frames with bad CRC that
D
C CRCerroriE When set, there is an interrupt if a
D
A IndividualA When set, frames with DA that
B
E ExtradataA When set, frames longer than 1518
E ExtradataiE When set, there is an interrupt if a
8
RxOKiE
Broad-
RuntA
RuntiE
castA
which
Table 20. Frame Acceptance Criteria
matches the IA at PacketPage base
+ 0158h are accepted*.
When set, all broadcast frames are
accepted*.
pass the DA filter are accepted.
When set, frames shorter than 64
bytes that pass the DA filter are
accepted.
bytes that pass the DA filter are
accepted (only the first 1518 bytes
are buffered).
Register 3, RxCFG
frame is received with valid length
and CRC*.
frame is received with bad CRC*.
When set, there is an interrupt if a
frame is received that is shorter than
64 bytes*.
frame is received that is longer than
1518 bytes*.
Register 5, RxCTL
When set, there is an interrupt if a
receive
Table 21.
events
Operation
Operation
will
cause
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