LAN8720AI-CP-TR SMSC, LAN8720AI-CP-TR Datasheet - Page 7

• Manufacturer Part Number: LAN8720AI-CP-TR
• Description: Ethernet ICs 10/100 Ethernet XCVR w/HP AutoMDIXSupport
• Manufacturer: SMSC

Specifications of LAN8720AI-CP-TR

• Product: Ethernet Transceivers
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support
Datasheet
Chapter 1 Introduction
SMSC LAN8720A/LAN8720Ai
1.1
1.2
BYTE
FIFO
MAC
RMII
N/A
X
RESERVED
SMI
TM
General Description
The following is list of the general terms used throughout this document:
The LAN8720A/LAN8720Ai is a low-power 10BASE-T/100BASE-TX physical layer (PHY) transceiver
with variable I/O voltage that is compliant with the IEEE 802.3-2005 standards.
The LAN8720A/LAN8720Ai supports communication with an Ethernet MAC via a standard RMII
interface. It contains a full-duplex 10-BASE-T/100BASE-TX transceiver and supports 10Mbps
(10BASE-T) and 100Mbps (100BASE-TX) operation. The LAN8720A/LAN8720Ai implements auto-
negotiation to automatically determine the best possible speed and duplex mode of operation. HP
Auto-MDIX support allows the use of direct connect or cross-over LAN cables.
The LAN8720A/LAN8720Ai supports both IEEE 802.3-2005 compliant and vendor-specific register
functions. However, no register access is required for operation. The initial configuration may be
selected via the configuration pins as described in
Register-selectable configuration options may be used to further define the functionality of the
transceiver.
Per IEEE 802.3-2005 standards, all digital interface pins are tolerant to 3.6V. The device can be
configured to operate on a single 3.3V supply utilizing an integrated 3.3V to 1.2V linear regulator. The
linear regulator may be optionally disabled, allowing usage of a high efficiency external regulator for
lower system power dissipation.
The LAN8720A/LAN8720Ai is available in both extended commercial and industrial temperature range
versions. A typical system application is shown in
General Terms and Conventions
8-bits
First In First Out buffer; often used for elasticity buffer
Media Access Controller
Reduced Media Independent Interface
Not Applicable
Indicates that a logic state is “don’t care” or undefined.
Refers to a reserved bit field or address. Unless otherwise noted, reserved
bits must always be zero for write operations. Unless otherwise noted, values
are not guaranteed when reading reserved bits. Unless otherwise noted, do
not read or write to reserved addresses.
Serial Management Interface
DATASHEET
7
Figure
Section 3.7, "Configuration Straps," on page
1.1.
TM
Revision 1.2 (11-10-10)
31.